METHODS OF ERASING SEMICONDUCTOR NON-VOLATILE MEMORIES

Abstract

For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Claims

1. A method of erasing a semiconductor nonvolatile memory (NVM) device, the semiconductor NVM device on a substrate comprising a source electrode, a drain electrode, a charge storage material and a control gate, the method comprising: applying a first voltage to the source electrode, the drain electrode and an electrode of the substrate; and applying a second voltage to an electrode of the control gate so that electrons tunnel from the charge storage material to the control gate; wherein the first voltage is less than or equal to zero and the second voltage is greater than or equal to zero; wherein the NVM device further comprises an tunneling dielectric film interposed between the charge storage material and the control gate, wherein the tunneling dielectric film comprises a first dielectric region and a second dielectric region, and a thickness of the first dielectric region is thicker than that of the second dielectric region, and wherein the step of applying the second voltage comprises: applying the second voltage to the electrode of the control gate so that the electrons tunnel from the charge storage material through the second dielectric region to the control gate.

2. The method according to claim 1, wherein a voltage difference between the control gate and the charge storage material is maximized if the following condition is satisfied: C.sub.cg=C.sub.cg1+C.sub.cg2<<C.sub.S+C.sub.sub+C.sub.D, where C.sub.cg denotes a control gate-to-charge storage material capacitance, C.sub.cg1 denotes a first capacitance of the first dielectric region of the tunneling dielectric film between the control gate and the charge storage material, C.sub.cg2 denotes a second capacitance of the second dielectric region of the tunneling dielectric film between the control gate and the charge storage material, C.sub.S denotes a source-to-charge storage material capacitance, C.sub.D a drain-to-charge storage material capacitance, and C.sub.sub denotes a substrate-to-charge storage material capacitance.

3. The method according to claim 2, wherein C.sub.cg is reduced as the thickness of the first dielectric region increases.

4. The method according to claim 2, wherein C.sub.cg is reduced as a size ratio of the first dielectric region to the second dielectric region increases.

5. The method according to claim 1, wherein a size of the first dielectric region is greater than that of the second dielectric region.

6. The method according to claim 1, wherein a magnitude of a first electrical field from the control gate through the first dielectric region to the charge storage material is less than a magnitude of a second electrical field from the control gate through the second electrical field region to the charge storage material.

7. The method according to claim 1, wherein the second dielectric region has an oxide thickness of 60 Ř300 Å.

8. The method according to claim 1, wherein the charge storing material is made of one selected from the group consisting of conducting floating gate, charge-trapping dielectric film and nano-crystal grains.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

[0013] FIG. 1 shows the schematic for the conventional F/N tunneling erase operation for semiconductor NVM devices.

[0014] FIG. 2 depicts the F/N tunneling occurring at the two edges of the control gate for a non-uniform lateral impurity concentration profile with high impurity concentrations on the two edge regions and low impurity concentrations in the middle region according to an embodiment of the invention.

[0015] FIG. 3 shows the electrical schematic for the semiconductor NVM device depicted in FIG. 2.

[0016] FIG. 4 illustrates the reduction of the electrical field in the tunneling dielectric for a low uniform impurity concentration control gate.

[0017] FIG. 5 shows the schematic for a semiconductor NVM device with two different dielectric thicknesses between the control gate and the floating gate according to another embodiment of the invention.

[0018] FIGS. 6a and 6b depict the idea of the Logic Gate NMV (LGNVM) device transformed from the conventional floating-gate (stacked double gates) NVM device.

[0019] FIG. 7a shows a top view of the LGNVM cell device array.

[0020] FIG. 7b shows a cross section view of impurity profiles for the control gates (wordline AA) of the LGNVM cell device array in FIG. 7a.

[0021] FIG. 8 shows the LGNVM electrical characteristics for the erase and programmed device by applying the erase scheme according to one embodiment of this invention.

[0022] FIG. 9a shows a top view of the conventional floating gate device with thick and thin tunneling dielectrics between the floating gate and control gate.

[0023] FIG. 9b shows a cross section view of the cut line AA′ in FIG. 9a.

DETAILED DESCRIPTION OF THE INVENTION

[0024] The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and structural changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having” and variations thereof herein is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0025] In one embodiment, we apply the erase operation scheme to the Logic Gate Non-Volatile Memory (LGNVM) devices as disclosed in U. S. Pat. No. 9,048,137 B2. The LGNVM device is similar to the conventional floating-gate NVM device with the structures of a single poly-gate as the floating gate and the control gate embedded in the silicon substrate fabricated with the standard CMOS logic technology process. FIG. 6b shows the capacitance coupling concept of LGNVM devices for folding the control gate of the conventional floating-gate NVM devices (FIG. 6a) into the silicon substrate. Referring to FIG. 6b, an N-type LGNVM device 60b includes a control gate 601b, a source electrode 602b, a substrate electrode 604b, a drain electrode 603b, a coupling dielectric 606b and a tunneling oxide 607b. For the N-type LGNVM device 60b, the N-type semiconductor control gate 601b is embedded in the P-type semiconductor substrate 604b. Referring to FIG. 6a, the conventional floating-gate NVM device 60a includes a control gate 601a, a source electrode 602a, a substrate electrode 604a, the drain electrode 603a, a coupling dielectric 606a and a tunneling oxide 607a. In contrast to the erase operation for the conventional floating-gate NVM devices 60a by applying a negative voltage (≥0V) to the control gate 601a and a positive voltage (≥0V) to the source electrode 602a, the substrate electrode 604a, and the drain electrode 603a, applying a negative high voltage to the control gates 601b of LGNVM devices 60b with source electrode 602b, the drain electrode 603b, and the substrate electrode 604b tied to a positive voltage (≥0V) is prohibited due to the forward biasing for the junctions of the embedded N-type control gate 601b and the P-type substrate 604b. The only option for applying a voltage bias on the N-type control gates 601b of LGNVM devices 60b is to apply a high positive voltage (≥0V) to the N-type control gates 601b of LGNVM devices 60b with other terminals (source/drain/substrate) tied to the zero voltage or negative voltages for the reverse biased junctions. For the erase operation, the maximum applicable control gate voltage bias is capped by the breakdown voltage for the junctions of the embedded N-type control gate 601b and the P-type substrate 604b. The low junction leakage current for the embedded N-type control gate applied with a positive voltage below the junction breakdown voltage is necessary for maintaining the applied positive voltage from the loading of the charge pumping circuitry for the F/N tunneling erase operation. It is very desirable for applying a lower positive control gate voltage with very low junction leakage currents between the N-type control gate 601b and the P-type substrate 604b to achieve the erase operation. In order to have a lower applied control gate voltage, we would like to have the most of the applied voltage difference generated in the tunneling dielectric 606b between the floating gate 605b and the control gate 601b. With this objective in mind, we engineer the lateral impurity profiles of the embedded N-type control gate near the substrate surfaces by adding extra high impurity concentration extension tips 712 under the two edges of the floating gate 710 for the embedded N-type control gate as shown in FIG. 7b.

[0026] FIG. 7a shows the top view of the LGNVM device and FIG. 7b shows the cross section view of the impurity profiles for the N-type control gates (wordline AA) of the LGNVM device in FIG. 7a. The N-type impurity profiles of the control gate with high concentration extension tips 712 (FIG. 7b) are formed without adding a new process by using the same fabrication process for the highly doped N-type extension of typical NMOSFET (N-type Metal Oxide Semiconductor Field Effect Transistor) devices in the deep submicron CMOS logic process technology. The fabrication process for the highly doped N-type extension of the typical NMOSFET in a deep submicron CMOS logic process is usually done by a low energy and high dose arsenic implant before the devices'spacer formation. FIG. 8 shows the LGNVM device electrical characteristics for the programed LGNVM device and the erased LGNVM device fabricated by the foundry's 40 nm CMOS logic process technology, where the Fowler-Nordheim tunneling erase operation can be only accomplished by the scheme of this invention.

[0027] In another embodiment, we apply the dielectric thickness increase on the major areas of the control gate for the floating-gate (stacked double-gates) semiconductor NVM cell device to reduce the total control gate-to-floating gate capacitance C.sub.cg for C.sub.S+C.sub.sub+C.sub.D>>C.sub.cg. FIG. 9a shows a top view of a typical floating-gate NOR flash array and FIG. 9b shows a cross section view of the control gates along a wordline (AA′ line in FIG. 9a). In the conventional floating-gate NVM fabrication process, the first dielectric film is deposited on the top of the floating gate 960 for the formation of coupling dielectrics before depositing the second poly-silicon film. In the embodiment, we can remove the first dielectric film for the areas inside the dash lines of the clear tone mask as shown in FIG. 9a. A thin tunneling dielectric of 60 Ř300 Å thick oxides can be then grown or deposited on to the removing areas of the first dielectric film to form the thin tunneling oxides in the thin tunneling oxide areas 910. When a row of control gates (a wordline) 930 is applied with a high positive voltage with the common source 920, bitline (drain electrodes) 940, and the substrate 950 tied to the ground voltage (0 V), the tunneling erase occurs in the thin tunneling oxide areas 910 between floating gate 960 and control gate 930.

[0028] Although the charge storage material in the above embodiments and examples are described herein in terms of floating gates, it should be understood that embodiments of the invention are not so limited, but are applicable to any type of the charge storage material, such as charge-trapping dielectric film and nano-crystal grains.

[0029] The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. Therefore, the term “the invention”, “the present invention” or the like is not necessary limited the claim scope to a specific embodiment, and the reference to particularly preferred exemplary embodiments of the invention does not imply a limitation on the invention, and no such limitation is to be inferred. The invention is limited only by the spirit and scope of the appended claims. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.