A variety of applications can include apparatus or methods that provide a well ring for resistive ground power domain segregation. The well ring can be implemented as a n-well in a p-type substrate. Resistive separation between ground domains can be generated by biasing a n-well ring to an external supply voltage. This approach can provide a procedure, from a process standpoint, that provides relatively high flexibility to design for chip floor planning and simulation, while providing sufficient noise rejection between independent ground power domains when correctly sized. Significant noise rejection between ground power domains can be attained.

A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the device includes a temperature sensor.

A non-volatile memory device comprises a memory cell region including a plurality of cell transistors, a first-type semiconductor substrate including a peripheral circuit region including circuits configured to control the plurality of cell transistors, and a plurality of pass transistors on the peripheral circuit region of the semiconductor substrate, wherein the peripheral circuit region includes a first region and a second region which are doped to a depth at an upper portion of the semiconductor substrate while being insulated from each other by an implant region, wherein the first region is a second type different from the first type, and includes a first doped region, and a first well region beneath the first doped region and configured to have a higher doping concentration than the first doped region, wherein the second region is the first type, and includes a second doped region, and a second well region beneath the second doped region and configured to have a higher doping concentration than the second doped region, wherein a first pass transistor on the first region from among the plurality of pass transistors is connected to a string selection line or a ground selection transistor, wherein a second pass transistor on the second region from among the plurality of pass transistors is connected to a word line, wherein a positive voltage or a negative voltage is configured to be applied to the second well region during operation of the second pass transistor.

A semiconductor structure includes semiconductor devices located on a top surface of a substrate semiconductor layer, lower-level metal interconnect structures embedded in lower-level dielectric material layers, source-level material layers, an alternating stack of insulating layers and electrically conductive layers overlying the source-level material layer, memory stack structures, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the alternating stack, an isolation trench fill structure interposed between the alternating stack and the vertically alternating sequence and including a trench fill material portion and a capping dielectric structure overlying the trench fill material portion, and a first through-memory-level interconnection via structure vertically extending through each plate within the vertically alternating sequence and contacting a top surface of one of the lower-level metal interconnect structures.

A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

The present technology provides a semiconductor device. The semiconductor device includes a stack including insulating patterns and conductive patterns stacked alternately with each other, a channel layer including a first channel portion protruding out of the stack and a second channel portion in the stack, and passing through the stack, and a conductive line surrounding the first channel portion, and the first channel portion includes metal silicide.

A semiconductor device includes: a semiconductor substrate (10) having a first region (NP1) and a second region (NP2); a first insulating layer (2b); a first gate electrode (3b) having a first semiconductor layer (31b) containing an impurity, a first conductive layer (32b) containing titanium, a second conductive layer (33b) containing nitrogen and either titanium or tungsten, and a third conductive layer (34b) containing tungsten; a second insulating layer (4b) provided on the third conductive layer and containing oxygen and silicon; a third insulating layer (5b) provided on the second insulating layer and containing nitrogen and silicon; a first contact (CS) provided on the first region; a second contact (CS) provided on the second region; and a third contact (C0) provided on the third conductive layer of the first gate electrode and penetrating through the second insulating layer and the third insulating layer.