A semiconductor device includes: a semiconductor substrate (10) having a first region (NP1) and a second region (NP2); a first insulating layer (2b); a first gate electrode (3b) having a first semiconductor layer (31b) containing an impurity, a first conductive layer (32b) containing titanium, a second conductive layer (33b) containing nitrogen and either titanium or tungsten, and a third conductive layer (34b) containing tungsten; a second insulating layer (4b) provided on the third conductive layer and containing oxygen and silicon; a third insulating layer (5b) provided on the second insulating layer and containing nitrogen and silicon; a first contact (CS) provided on the first region; a second contact (CS) provided on the second region; and a third contact (C0) provided on the third conductive layer of the first gate electrode and penetrating through the second insulating layer and the third insulating layer.

A semiconductor device includes a first semiconductor structure, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a substrate having first and second regions, gate electrodes spaced apart from each other on the first region, extending by different lengths and respectively including a pad region having an upper surface exposed upwardly, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes, gate contact plugs penetrating through the pad region of each of the gate electrodes and extending into the first semiconductor structure, and an insulating structure alternating with the interlayer insulating layers below each of the pad regions and surrounding the gate contact plugs. The insulating structure includes a first insulating layer and a second insulating layer surrounding at least a portion of the first insulating layer and including a material different from any of the first insulating layer.

A semiconductor device includes a first semiconductor structure, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a substrate having first and second regions, gate electrodes spaced apart from each other on the first region, extending by different lengths and respectively including a pad region having an upper surface exposed upwardly, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes, gate contact plugs penetrating through the pad region of each of the gate electrodes and extending into the first semiconductor structure, and an insulating structure alternating with the interlayer insulating layers below each of the pad regions and surrounding the gate contact plugs. The insulating structure includes a first insulating layer and a second insulating layer surrounding at least a portion of the first insulating layer and including a material different from any of the first insulating layer.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A semiconductor device includes a first stack structure including first interlayer insulating layers and first conductive patterns alternately stacked on each other in a first direction and a second conductive pattern comprising electrode portions and a connecting portion. The electrode portions of the second conductive pattern are stacked to be spaced apart from each other above the first stack structure. The connecting portion of the second conductive pattern extends in the first direction to intersect the electrode portions and couples the electrode portions. The semiconductor device further includes a vertical channel and a vertical conductive structure that pass through the first stack structure and the electrode portions of the second conductive pattern. The vertical conductive structure is spaced apart from the first stack structure and the second conductive pattern.

Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is =on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.