Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

A semiconductor device includes a cell substrate including a cell array region and an extension region surrounding the cell array region, a mold structure including gate electrodes sequentially stacked on the cell substrate, channel structures disposed on the cell array region and intersecting the gate electrodes, a bit-line connected to at least some of the channel structures, a block isolation region cutting the mold structure, a source layer disposed between the cell substrate and the mold structure and connected to a side surface of each of the channel structures, and a support layer disposed between the source layer and the mold structure on upper surfaces of the cell substrate and the source layer. The support layer includes a support structure contacting the upper surface of the cell substrate. The support structure includes a peripheral portion surrounding the cell array region, and a mesh portion disposed on the extension region.

A semiconductor device includes a cell substrate including a cell array region and an extension region surrounding the cell array region, a mold structure including gate electrodes sequentially stacked on the cell substrate, channel structures disposed on the cell array region and intersecting the gate electrodes, a bit-line connected to at least some of the channel structures, a block isolation region cutting the mold structure, a source layer disposed between the cell substrate and the mold structure and connected to a side surface of each of the channel structures, and a support layer disposed between the source layer and the mold structure on upper surfaces of the cell substrate and the source layer. The support layer includes a support structure contacting the upper surface of the cell substrate. The support structure includes a peripheral portion surrounding the cell array region, and a mesh portion disposed on the extension region.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.

A semiconductor memory device includes: a semiconductor substrate including a first region and a second region; a memory cell array over the first region of the semiconductor substrate; a dummy stack structure over the second region of the semiconductor substrate; a chip guard structure penetrating the dummy stack structure; and a void-containing structure penetrating the dummy stack structure.

A semiconductor memory device includes: a semiconductor substrate including a first region and a second region; a memory cell array over the first region of the semiconductor substrate; a dummy stack structure over the second region of the semiconductor substrate; a chip guard structure penetrating the dummy stack structure; and a void-containing structure penetrating the dummy stack structure.

A semiconductor device includes a lower structure, stack structure including gate electrodes stacked and spaced apart from each other on a first region of the lower structure and extending in a staircase shape on a second region of the lower structure, and interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes on the first region, and isolation structures penetrating through the gate electrodes spaced apart from each other. Each channel structure a channel bent portion between first and second channel structures. Each isolation structure includes a first isolation bent portion between first and second isolation structures and a second isolation bent portion between second and third isolation structures. A width of an upper surface of the second isolation structure is narrower than a width of a lower surface of the third isolation structure.