Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, and a source contact above the memory stack and in contact with the P-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the P-type doped semiconductor layer.

Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

A semiconductor device includes gate electrodes stacked to be spaced apart from each other on a substrate in a first direction, extending in a second direction, and including pad regions bent in a third direction, sacrificial insulating layers extending from the gate electrodes to be stacked alternately with the interlayer insulating layers, separation regions penetrating through the gate electrodes, extending in the second direction, and spaced apart from each other to be parallel to each other, and a through-wiring region spaced apart from the separation regions to overlap the pad regions between the separation regions adjacent to each other and including contact plugs penetrating through the pad regions. The through-wiring region includes slit regions, and each of the slit regions is disposed to penetrate through the sacrificial insulating layers on one side of a respective pad region.

A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

A nonvolatile memory device includes; a memory cell area including a cell structure and a common source plate. The memory cell area is mounted on a peripheral circuit area including a buried area covered by the memory cell area and an exposed area uncovered by the memory cell area. A first peripheral circuit (PC) via extending from the exposed area, and a common source (CS) via extending from the common source plate, wherein the first PC via and the CS via are connected by a CS wire disposed outside the cell structure and providing a bias voltage to the common source plate.

In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on a substrate; a plurality of channel structures penetrating the gate stack structure, each of the plurality of channel structures with one end portion protruding past a boundary of the gate stack structure; and a source layer formed on the gate stack structure. The protruding end portion of each of the plurality of channel structures extends into the source layer. The protruding end portion of each of the plurality of channel structures has a flat section.

A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.

A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.