A semiconductor device includes a cell substrate including a cell array region and an extension region surrounding the cell array region, a mold structure including gate electrodes sequentially stacked on the cell substrate, channel structures disposed on the cell array region and intersecting the gate electrodes, a bit-line connected to at least some of the channel structures, a block isolation region cutting the mold structure, a source layer disposed between the cell substrate and the mold structure and connected to a side surface of each of the channel structures, and a support layer disposed between the source layer and the mold structure on upper surfaces of the cell substrate and the source layer. The support layer includes a support structure contacting the upper surface of the cell substrate. The support structure includes a peripheral portion surrounding the cell array region, and a mesh portion disposed on the extension region.

A semiconductor memory device includes: a semiconductor substrate including a first region and a second region; a memory cell array over the first region of the semiconductor substrate; a dummy stack structure over the second region of the semiconductor substrate; a chip guard structure penetrating the dummy stack structure; and a void-containing structure penetrating the dummy stack structure.

A semiconductor device includes a lower structure, stack structure including gate electrodes stacked and spaced apart from each other on a first region of the lower structure and extending in a staircase shape on a second region of the lower structure, and interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating through the gate electrodes on the first region, and isolation structures penetrating through the gate electrodes spaced apart from each other. Each channel structure a channel bent portion between first and second channel structures. Each isolation structure includes a first isolation bent portion between first and second isolation structures and a second isolation bent portion between second and third isolation structures. A width of an upper surface of the second isolation structure is narrower than a width of a lower surface of the third isolation structure.

A semiconductor device and a method of manufacturing the semiconductor includes a first source layer spaced apart from a substrate and disposed in a memory cell region of the substrate, a second source layer spaced apart from the substrate and disposed in a contact region of the substrate, a cell stacked structure including interlayer insulating layers and conductive patterns alternately stacked on each other over the first source layer, a discharge contact passing through at least a part of the second source layer, and a dielectric layer disposed between the second source layer and the discharge contact.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.

A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.

A vertical-type nonvolatile memory device including: a substrate including a cell array area and an extension area, the extension area extending in a first direction from the cell array area and including contacts; a channel structure extending in a vertical direction from the substrate; a first stack structure including gate electrode layers and interlayer insulating layers alternately stacked along sidewalls of the channel structure; a plurality of division areas extending in the first direction and dividing the cell array area and the extension area in a second direction perpendicular to the first direction; in the extension area, two insulating layer dams are arranged between two division areas adjacent to each other; a second stack structure including sacrificial layers and interlayer insulating layers alternately stacked on the substrate between the two insulating layer dams; and an electrode pad connected to a first gate electrode layer in the extension area.

A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.