A semiconductor storage device includes a memory cell array including a stacked body having insulating layers and conductive layers that are alternately stacked. The memory cell array includes a cell area and a contact area provided adjacent the cell area. The semiconductor storage device includes: a circuit below the memory cell array; a source layer between the memory cell array and the circuit; a first contact in the contact area, and coupled to the circuit; a second contact over the cell area and the contact area; a first wiring extending in a direction intersecting an extending direction of the second contact in the contact area; a second wiring above the second contact, extending along the second contact in the contact area, and connected to the first wiring; and third contacts between the second wiring and the second contact.

A semiconductor storage device includes a memory cell array including a stacked body having insulating layers and conductive layers that are alternately stacked. The memory cell array includes a cell area and a contact area provided adjacent the cell area. The semiconductor storage device includes: a circuit below the memory cell array; a source layer between the memory cell array and the circuit; a first contact in the contact area, and coupled to the circuit; a second contact over the cell area and the contact area; a first wiring extending in a direction intersecting an extending direction of the second contact in the contact area; a second wiring above the second contact, extending along the second contact in the contact area, and connected to the first wiring; and third contacts between the second wiring and the second contact.

A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a stack structure includes interleaved dielectric layers and conductive layers, a channel structure extending in the stack structure, and a doped semiconductor layer arranged on the stack structure. The doped semiconductor layer covers an end of the channel structure and the stack structure, the channel structure includes a channel layer, and the channel layer includes a doped channel layer.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a stack structure including conductive patterns and interlayer insulating layers, which are alternately stacked in a first direction; a channel layer penetrating the stack structure; a first semiconductor layer disposed on the stack structure, the first semiconductor layer including a first impurity of a first conductivity type; a second semiconductor layer disposed on the first semiconductor layer, the second semiconductor layer including a well region with a second impurity of a second conductivity type, wherein the second conductivity type is different from the first conductivity type; and a memory layer between the channel layer and the stack structure.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of memory cells including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells including a second transistor, and a third semiconductor layer in contact with the second transistor. The second semiconductor layer is between the first bonding interface and the first peripheral circuit. The third semiconductor layer is between the second bonding interface and the second peripheral circuit.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

A three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure. A first semiconductor structure includes a first substrate, and a memory array structure disposed on the first substrate. The second semiconductor structure is disposed over the first semiconductor structure, and the second semiconductor structure includes a second substrate, and a peripheral device in contact with the second substrate. The second substrate is formed between the peripheral device and the first semiconductor structure.

A three-dimensional (3D) memory device includes a first substrate, a first semiconductor structure, and a second semiconductor structure. The first semiconductor structure is disposed on the first substrate. The first semiconductor structure includes a second substrate, and a peripheral device disposed over the second substrate, and the peripheral device is formed facing the first substrate. The second semiconductor structure is disposed on the first semiconductor structure. The second semiconductor structure includes a doped semiconductor layer, and a memory array structure disposed between the doped semiconductor layer and the first semiconductor structure.