A semiconductor device is disclosed. The semiconductor device includes a first slit, at least one word line, and a second slit. The first slit is disposed at a boundary between contiguous memory blocks to isolate the memory blocks from each other, and includes a first outer slit and a second outer slit, the second outer slit is spaced apart in a first direction from the first outer slit by a predetermined distance. The word line is disposed, between the first and second outer slits, including a center region having a first end and a second end, and an edge region located at the first end and a second end of the center region, and the second slit is disposed at the center region that isolate area of the word line in the center region on either side of the second slit, wherein the word line is continuous in the edge regions.

A memory device and a manufacturing for the same are provided. The memory device comprises a channel line, word lines, a first switch, and a second switch. Memory cells for a memory string are defined at intersections between the channel line and the word lines. The first switch is electrically connected with the channel line. The second switch is electrically connected with the channel line. The first switch is electrically connected between the second switch and the memory cells.

A memory device with a three-dimensional (3D) staircase memory stack includes dummy connectors proximate semi-isolated connectors. The memory device includes multiple wordlines stacked in a 3D staircase stack, which includes a wordline at an edge of a region of the staircase. The memory device includes vertical connectors through an isolation layer on the 3D staircase stack to connect the wordlines with conductive lines in an access layer. A wordline at the edge of the region of the staircase has a vertical connector that will be adjacent a connector on one side and not on the other side. The memory device includes at least one dummy vertical connector on the edge side of the vertical connector of the wordline on the edge, wherein the dummy vertical connector does not electrically connect a wordline of the 3D staircase stack to a conductive line in the access layer.

The present application provides a three-dimensional memory and a fabrication method for the same. The method includes forming a storage stack structure on a substrate and forming a storage channel structure that penetrates the storage stack structure, forming a selection stack structure stacked on the storage stack structure and forming a selection channel structure that penetrates the selection stack structure and is connected to the storage channel structure. The width of the selection channel structure is smaller than the width of the storage channel structure on a plane parallel to the substrate and forming a TSG cut structure that penetrates the selection stack structure. The three-dimensional memory and the fabrication method for the same increases the process window for the TSG cut structure formed between the selection channel structures and improves the storage density.

A method includes disposing a layer stack on a substrate, the layer stack including a number of levels. A first control gate structure is formed in a first level of the number of levels by: forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level; removing a remaining portion of the sacrificial layer of the first level to form a first cavity; and disposing a first conductive layer in the first cavity. A second control gate structure is formed in a second level below the first level by: extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening; removing a remaining portion of the sacrificial layer of the second level to form a second cavity; and disposing a second conductive layer in the second cavity.

A memory device includes a staircase structure, multiple first plugs, multiple second plugs, and multiple third plugs. The staircase structure includes multiple gate layers and multiple insulating layers alternately stacked on each other, and the staircase structure includes multiple first blocks and multiple second blocks which alternate with each other. The first plugs are disposed in the first blocks, and the first plugs in a same first block are staggered with each other. The second plugs are disposed in the first blocks. The second plugs in a same first block are staggered with each other, and the first plugs and the second plugs in a same first block are staggered with each other. The third plugs are disposed in the second blocks.

A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

A semiconductor device includes a substrate; a first stack structure including first gate electrodes on the substrate; and a second stack structure on the first stack structure; wherein the first stack structure includes a first lower staircase region, a second lower staircase region, and a third lower staircase region, wherein the second stack structure includes a first upper staircase region, a second upper staircase region, a third upper staircase region, and at least one through portion penetrating the second stack structure and on the first to third lower staircase regions, wherein the first lower staircase region has a same shape as a shape of the first upper staircase region, the second lower staircase region has a same shape as a shape of the second upper staircase region, and the third lower staircase region has a same shape as a shape of the third upper staircase region.

A vertical repetition of multiple instances of a unit layer stack is formed over a substrate. The unit layer stack includes an insulating layer and a sacrificial material layer. Lateral recesses are formed by removing the sacrificial material layers selective to the insulating layers. Each lateral recess is sequentially fill with at least one conductive fill material and an insulating fill material, and vertically-extending portions of the at least one conductive fill material are removed such that a vertical layer stack including a first-type electrically conductive layer, a seamed insulating layer, and a second-type electrically conductive layer are formed in each lateral recess. Memory opening fill structures including a respective vertical stack of memory elements is formed through the insulating layers and the layer stacks. Access points for providing an etchant for removing the sacrificial material layers may be provided by memory openings, contact via cavities or backside trenches.

A microelectronic device comprises a stack structure, contact structures, and additional contact structures. The stack structure comprises a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure is divided into blocks each comprising a stadium structure including steps comprising horizontal ends of the tiers. The contact structures are within a horizontal area of the stadium structure and vertically extend through the stack structure. The additional contact structures are on at least some of the steps of the stadium structure and are coupled to the contact structures. Memory devices and electronic devices are also disclosed.