A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.

A vertical repetition of a unit layer stack includes an insulating layer, a first sacrificial material layer, another insulating layer, and a second sacrificial material layer. A memory opening is formed through the vertical repetition, and a memory opening fill structure is formed in the memory opening. A backside trench is formed through the alternating stack. The first sacrificial material layers are replaced with first electrically conductive layers, and the second sacrificial material layer are replaced with second electrically conductive layers after formation of the first electrically conductive layers.

A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity.

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.

A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.

A ferroelectric memory device includes interlayer insulating layers and gate lines alternately stacked, a data storage layer vertically passing through the interlayer insulating layers and the gate lines and having a cylindrical shape, and a channel layer formed in an area enclosed by the data storage layer. The data storage layer includes a first ferroelectric layer abutting on the channel layer, a second ferroelectric layer abutting on the interlayer insulating layers and the gate lines, and an interface layer formed between the first and the second ferroelectric layers.

Provided is a memory cell including a channel material contacting a source line and a bit line; a ferroelectric (FE) material contacting the channel material; and a word line contacting the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer; and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.