A three-dimensional memory device includes a first electrode structure and a second electrode structure extending in a first direction, being adjacent to each other in a second direction intersecting with the first direction, and each including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a source plate; a plurality of first slimming holes formed in the first electrode structure to expose pad regions of the electrode layers of the first electrode structure, and arranged in the first direction; and a plurality of second slimming holes formed in the second electrode structure to expose pad regions of the electrode layers of the second electrode structure, and arranged in the first direction, wherein a first slimming hole and a second slimming hole which are adjacent in the second direction have different depths.

A semiconductor device includes, a substrate including a cell region and a peripheral circuit region; a vertical structure extending perpendicular to an upper surface of the substrate, the vertical structure including a bit line and a source line spaced apart in a first direction; a word line extending in the first direction; a channel layer between the bit line and the word line, and between the source line and the word line, the channel layer connected between the bit line and the source line; a ferroelectric layer between the word line and the channel layer; a control circuit on the substrate; a source line connection wire connected to the source line and the control circuit; and a bit line connection wire connected to the bit line and the control circuit. The source line connection wire and the bit line connection wire cross on a plane.

A semiconductor device includes, a substrate including a cell region and a peripheral circuit region; a vertical structure extending perpendicular to an upper surface of the substrate, the vertical structure including a bit line and a source line spaced apart in a first direction; a word line extending in the first direction; a channel layer between the bit line and the word line, and between the source line and the word line, the channel layer connected between the bit line and the source line; a ferroelectric layer between the word line and the channel layer; a control circuit on the substrate; a source line connection wire connected to the source line and the control circuit; and a bit line connection wire connected to the bit line and the control circuit. The source line connection wire and the bit line connection wire cross on a plane.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

A three-dimensional memories is provided. The three-dimensional memories includes a plurality of transistors arranged in multiple levels that are stacked in a first direction. The transistors are arranged in lines within each of the levels, the lines extend in a second direction different than the first direction. Each of the transistors includes a channel, a memory film surrounding the channel, and a gate electrode surrounding the memory film. The channels of the transistors in two adjacent lines in the same level are staggered. The three-dimensional memory further includes a plurality of word lines electrically coupled to the gate electrodes of the transistors.

A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.

A 3D memory array includes a tableland feature formed with multiple 3D memory sub-arrays that are arranged in an X-axis direction. Each 3D memory sub-array includes multiple memory cells that are distributed in multiple columns arranged in the X-axis direction, multiple bit lines extending in a Z-axis direction, multiple source lines extending in the Z-axis direction, and multiple word lines extending in a Y-axis direction. Each memory cell includes a first electrode, a second electrode and a gate electrode. Each bit line interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction. Each bit line is electrically connected to another bit line of the same 3D memory sub-array, which is aligned with the bit line in the X-axis direction, and is electrically isolated from the bit lines of another 3D memory sub-array.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.

Some embodiments include an integrated assembly having first and second pillars of semiconductor material. The first pillar includes a first source/drain region, and the second pillar includes a second source/drain region. First and second bottom electrodes are coupled with the first and second source/drain regions, respectively. The first and second source/drain regions are spaced from one another by an intervening region. First and second leaker-device-structures extend into the intervening region from the first and second bottom electrodes, respectively. Top-electrode-material extends into the intervening region and contacts the first and second leaker-device-structures. Ferroelectric-insulative-material is between the top-electrode-material and the bottom electrodes. Some embodiments include methods of forming integrated assemblies.