A memory device includes a multi-layer stack, a channel layer, a memory material layer and at least three conductive pillars. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer and memory material layer penetrate through the plurality of conductive layers and the plurality of dielectric layers. The at least three conductive pillars are surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive layers respectively. The at least three conductive pillars includes a first, a second and a third conductive pillars disposed between the first conductive pillar and the second conductive pillar. A third width of the third conductive pillar is smaller than a first width of the first conductive pillar and a second width of the second conductive pillar.

A method of memory device fabrication includes, providing a structure that includes first layers including word lines interleaved respectively with first dielectric layers, second layers including second dielectric layers interleaved respectively with the first dielectric layers, wherein the second layers are adjacent to the first layers, forming vertical recesses each of which extend to a surface of a respective one of the second dielectric layers in a first direction through the second layers, etching a respective lateral recess to expose a surface of a respective one of the word lines, and filling each respective lateral recess with at least one conductive material, such that the at least one conductive material in the respective lateral recess is in contact with the respective one of the word lines through the exposed surface.