Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

A semiconductor storage device includes a stacked body and a columnar body. The stacked body includes a plurality of conductive layers spaced apart from each other in a stacking direction. The columnar body penetrates the stacked body in the stacking direction. The columnar body includes a columnar ferroelectric film, a semiconductor film disposed between the ferroelectric film and the conductive layers, and an insulating film disposed between the semiconductor film and the conductive layers.

A semiconductor device includes: a first common plate extending vertically in a first direction; a second common plate which is spaced apart from the first common plate in a second direction and extends vertically in the first direction; a slit formed between the first common plate and the second common plate; a first memory cell array sharing the first common plate and including first capacitors that are vertically stacked in the first direction; and a second memory cell array sharing the second common plate and including second capacitors that are vertically stacked in the first direction.

A semiconductor device includes: a first common plate extending vertically in a first direction; a second common plate which is spaced apart from the first common plate in a second direction and extends vertically in the first direction; a slit formed between the first common plate and the second common plate; a first memory cell array sharing the first common plate and including first capacitors that are vertically stacked in the first direction; and a second memory cell array sharing the second common plate and including second capacitors that are vertically stacked in the first direction.

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

Embodiments of ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a method of forming a ferroelectric memory cell is disclosed. A first electrode is formed. A doped ferroelectric layer is formed in contact with the first electrode. The doped ferroelectric layer includes oxygen and one or more ferroelectric metals. The doped ferroelectric layer further includes a plurality of dopants including at least one dopant from one of Group II elements, Group III elements, or Lanthanide elements. The plurality of dopants are different from the one or more ferroelectric metals. A second electrode is formed in contact with the doped ferroelectric layer.

In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.