A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of memory cells each including a transistor and a capacitor, and capacitors included in adjacent memory cells are provided to overlap with each other. A first capacitor included in a first memory cell is provided so as to partly overlap with a second memory cell adjacent to the first memory cell. A second capacitor included in a second memory cell and the first capacitor are provided over different layers. The second capacitor is provided so as to partly overlap with the first memory cell. The first capacitor and the second capacitor include a region where they overlap with each other. The first and second capacitors include a ferroelectric. The ferroelectric preferably includes hafnium, zirconium, or at least one element selected from Group III-V elements. The transistor preferably includes an oxide semiconductor in a semiconductor layer where a channel is formed.

The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode.

Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.

Provided is a semiconductor storage device and an electronic apparatus having a structure that is more suitable for miniaturization and high integration of memory cells. A semiconductor storage device includes: a recessed portion provided in a semiconductor substrate; a ferroelectric film provided along an inner side of the recessed portion; an electrode provided on the ferroelectric film so as to be embedded in the recessed portion; a first conductivity-type separation region provided in the semiconductor substrate under the recessed portion; and a second conductivity-type electrode region provided in the semiconductor substrate on at least one side of the recessed portion.

Some embodiments include an integrated assembly having first electrodes with top surfaces, and with sidewall surfaces extending downwardly from the top surfaces. The first electrodes are solid pillars. Insulative material is along the sidewall surfaces of the first electrodes. Second electrodes extend along the sidewall surfaces of the first electrodes and are spaced from the sidewall surfaces by the insulative material. Conductive-plate-material extends across the first and second electrodes, and couples the second electrodes to one another. Leaker-devices electrically couple the first electrodes to the conductive-plate-material and are configured to discharge at least a portion of excess charge from the first electrodes to the conductive-plate-material. Some embodiments include methods of forming integrated assemblies.

A ferroelectric memory device according to an embodiment includes a base conduction layer, a channel layer extending in a vertical direction from the base conduction layer, a ferroelectric layer disposed on the channel layer, a plurality of ferroelectric memory cell transistor stacked in a vertical direction on the base conduction layer, a control transistor disposed over the plurality of ferroelectric memory cell transistors, and a bit line pattern electrically connected to the channel layer.