A method of forming a memory device including forming a stack of silicon nitride layers and polysilicon layers that are alternating arranged, etching a serpentine trench in the stack of silicon nitride layers and polysilicon layers, forming a first isolation layer in the serpentine trench, removing one of the silicon nitride layers to form a recess between neighboring two of the polysilicon layers, and forming in sequence a doped polysilicon layer, a gate dielectric layer, and a conductive layer in the recess.

A method of forming an array of capacitors comprises forming a plurality of horizontally-spaced groups that individually comprise a plurality of horizontally-spaced lower capacitor electrodes having a capacitor insulator thereover. Adjacent of the groups are horizontally spaced farther apart than are adjacent of the lower capacitor electrodes within the groups. A void space is between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the groups over the capacitor insulator and the lower capacitor electrodes. The upper capacitor electrode material in the void space connects the upper capacitor electrode material that is in the adjacent groups relative to one another. The upper capacitor electrode material less-than-fills the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent groups from being connected relative to one another. A horizontally-elongated conductive line is formed atop and is directly electrically coupled to the upper capacitor electrode material in individual of the groups. Other methods, including structure independent of method of manufacture, are disclosed.

In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.

A transistor includes a substrate having a plurality of source/drain regions and a channel region between the source/drain regions, a gate, and a gate dielectric layer between the gate and the substrate. The substrate tapers in a direction away from the gate dielectric layer in top view. The transistor density can be improved.

An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (FET), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second access terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

In a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, a stacked structure including interlayer insulating layers and interlayer sacrificial layers that are alternately stacked is formed on a substrate. A trench is formed passing through the stacked structure on the substrate. A crystalline liner insulating layer is formed on a sidewall of the trench. A ferroelectric insulating layer and a channel layer are formed on the crystalline liner insulating layer. The interlayer sacrificial layers and the crystalline liner insulating layer are selectively removed to form a recess selectively exposing the ferroelectric insulating layer. The recess is filled with a conductive layer to form an electrode layer.

Some embodiments include an integrated memory having an array of capacitors. The array has edges. The capacitors along the edges are edge capacitors, and the other capacitors are internal capacitors. The edge capacitors have inner edges facing toward the internal capacitors, and have outer edges in opposing relation to the inner edges. An insulative beam extends laterally between the capacitors. The insulative beam is along upper regions of the capacitors. First void regions are under the insulative beam, along lower regions of the internal capacitors, and along the inner edges of the edge capacitors. Peripheral extensions of the insulative beam extend laterally outward of the edge capacitors, and second void regions are under the peripheral extensions and along the outer edges of the edge capacitors. Some embodiments included integrated assemblies having two or more memory array decks stacked on atop another. Some embodiments include methods of forming memory arrays.