The invention provides a semiconductor structure, which comprises a substrate with at least a first transistor and a second transistor, and a capacitor structure in a dielectric layer above the substrate, wherein the capacitor structure is electrically connected with a gate of the first transistor and a drain of the second transistor.

The invention provides a semiconductor structure, which comprises a substrate with at least a first transistor and a second transistor, and a capacitor structure in a dielectric layer above the substrate, wherein the capacitor structure is electrically connected with a gate of the first transistor and a drain of the second transistor.

A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.

A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode and implementing a negative capacitance, a dielectric structure disposed on the ferroelectric layer and including a first dielectric layer and a second dielectric layer that are alternately stacked, and a second electrode disposed on the dielectric structure. The ferroelectric layer and the dielectric structure are configured to be electrically connected in series to each other. The ferroelectric layer and dielectric structure together have a non-ferroelectric property.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, having a first surface; a plurality of memory cells, located on the first surface of the substrate and arranged according to a first preset pattern; and a plurality of memory contact structures, corresponding to the memory cells in a one-to-one manner, where bottom portions of the memory contact structures are in contact with top portions of the memory cells, and top portions of the memory contact structures are arranged according to a second preset pattern. The bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.

A capacitor includes: a bottom electrode; a top electrode; and a hybrid dielectric layer including at least one nanosheet material disposed between the bottom electrode and the top electrode.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to ferroelectric random access memory (FRAM) devices with an enhanced capacitor architecture. Other embodiments may be disclosed or claimed.

A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.

The present disclosure provides a memory circuit, a memory device and an operating method of the memory device. The memory device includes a storage transistor, a variable capacitance device and a control transistor. The variable capacitance device is electrically connected to the gate of the storage transistor, and the control transistor is connected to the storage transistor in series.