Provided is a nonvolatile memory device including a lower electrode on a substrate, an upper electrode on the lower electrode, a tunnel barrier pattern between the lower electrode and the upper electrode, and a fixed charge pattern in contact with the lower electrode and spaced apart from the tunnel barrier pattern with the lower electrode therebetween. The tunnel barrier pattern includes an anti-ferroelectric material. The lower electrode includes a first material. The upper electrode includes a second material. The first material and the second material have different work functions.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, to memory devices having ferroelectric capacitors coupled between intersecting bitlines and wordlines. Other embodiments may be disclosed or claimed.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, to memory devices having ferroelectric capacitors coupled between intersecting bitlines and wordlines. Other embodiments may be disclosed or claimed.

An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Methods, systems, and devices for deck selection layouts in a memory device are described. In some implementations, a tile of a memory array may be associated with a level above a substrate, and may include a set of memory cells, a set of digit lines, and a set of word lines. Selection transistors associated with a tile of memory cells may be operable for coupling digit lines of the tile with circuitry outside the tile, and may be activated by various configurations of one or more access lines, where the various configurations may be implemented to trade off or otherwise support design and performance characteristics such as power consumption, layout complexity, operational complexity, and other characteristics. Such techniques may be implemented for other aspects of tile operations, including memory cell shunting or equalization, tile selection using transistors of a different level, or signal development, or various combinations thereof.

A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.