To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

A method of forming memory circuitry comprises using a digitline mask to form both: (a) conductive digitlines in a memory array area, and (b) lower portions of conductive vias in a peripheral circuitry area laterally of the memory array area. The lower portions of the vias electrically couple with circuitry below the vias and the digitlines. Pairs of conductive wordlines are formed above the digitlines in the memory array area. The pairs of wordlines extend from the memory array area into the peripheral circuitry area. Individual of the pairs are directly above individual of the lower portions of individual of the vias. Individual upper portions of the individual vias are formed. The individual upper portions both: (c) directly electrically couple to one of the individual lower portions of the individual vias, and (d) directly electrically couple together the wordlines of the individual pair of wordlines that are directly above the respective one individual lower portion of the respective individual via. Other methods, and structure independent of method of fabrication, are disclosed.

A method for co-manufacturing a FeRAM and an OxRAM includes depositing a layer of first electrode carried out identically for a zone Z1 and a zone Z2; depositing a layer of hafnium dioxide-based active material carried out identically for Z1 and Z2; depositing a first conductive layer carried out identically for Z1 and Z2; making a mask at Z2, leaving Z1 free; removing the layer at Z1, with Z2 being protected by the mask; removing the mask at Z2; and depositing a second conductive layer in contact with the layer at Z2 and in contact with the layer at Z1, the material of the layer being chosen to create oxygen vacancies in the active layer and depositing a third conductive layer carried out identically for Z1 and Z2.

A plurality of vertical stacks may be formed over a substrate. Each of the vertical stacks includes, from bottom to top, a bottom electrode, a dielectric pillar, and a top electrode. A continuous active layer and a gate dielectric layer may be formed over the plurality of vertical stacks. Sacrificial spacers are formed around the plurality of vertical stacks. At least one dielectric wall structure may be formed around the sacrificial spacers by filling gaps between neighboring pairs of the sacrificial spacers with a dielectric fill material. The sacrificial spacers are replaced with gate electrodes. Each of the gate electrodes may laterally surround a respective row of vertical stacks that are arranged along a first horizontal direction.

A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

To compensate switching of a dielectric component of a non-linear polar material based capacitor, an explicit dielectric capacitor is added to a memory bit-cell and controlled by a signal opposite to the signal driven on a plate-line.

In certain aspects, a memory device includes a vertical transistor including a semiconductor body extending in a first direction, a stack structure including interleaved dielectric layers and conductive layers each extending perpendicularly to the first direction, an electrode layer including a conductive material and coupled to a first end of the semiconductor body, and a storage layer over the electrode layer. The electrode layer and the storage layer extend in the first direction through the stack structure.