A memory cell circuit is provided that may include: a memory cell, the memory cell including a ferroelectric structure; a first control terminal and a second control terminal connected to the memory cell, the first control terminal and the second control terminal being configured to allow an operation of the memory cell; and a first auxiliary terminal and a second auxiliary terminal connected to the memory cell, the first auxiliary terminal and the second auxiliary terminal being configured to provide an auxiliary voltage to the ferroelectric structure.

Provided is a semiconductor device including a dielectric layer, a first via, a second via, a first barrier layer, and a second barrier layer. The dielectric layer has a first region and a second region. The first via is disposed in the dielectric layer in the first region. The second via is disposed in the dielectric layer in the second region. The first barrier layer lines a sidewall and a bottom surface of the first via. The second barrier layer lines a sidewall and a bottom surface of the second via. The first and second barrier layers each has an upper portion and a lower portion. The upper portion has a nitrogen doping concentration greater than a nitrogen doping concentration of the lower portion. A method of manufacturing a semiconductor device is also provided.

One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.

Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder may include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder may include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

An integrated circuit construction comprising memory comprises two memory-cell-array regions having a peripheral-circuitry region laterally there-between in a vertical cross-section. The two memory-cell-array regions individually comprise a plurality of capacitors individually comprising a capacitor storage node electrode, a shared capacitor electrode that is shared by the plurality of capacitors, and a capacitor insulator there-between. A laterally-extending insulator structure is about lateral peripheries of the capacitor storage node electrodes and is vertically spaced from a top and a bottom of individual of the capacitor storage node electrodes in the vertical cross-section. The peripheral-circuitry region in the vertical cross-section comprises a pair of elevationally-extending walls comprising a first insulative composition. A second insulative composition different from the first insulative composition is laterally between the pair of walls. The pair of walls individually have a laterally-outer side of the first insulative composition that is directly against a lateral edge of the insulator structure that is in different ones of the two array regions. Other embodiments, including methods, are disclosed.

A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

Methods and apparatuses for thin film transistors and related fabrication techniques are described. The thin film transistors may access two or more decks of memory cells disposed in a cross-point architecture. The fabrication techniques may use one or more patterns of vias formed at a top layer of a composite stack, which may facilitate building the thin film transistors within the composite stack while using a reduced number of processing steps. Different configurations of the thin film transistors may be built using the fabrication techniques by utilizing different groups of the vias. Further, circuits and components of a memory device (e.g., decoder circuitry, interconnects between aspects of one or more memory arrays) may be constructed using the thin film transistors as described herein along with related via-based fabrication techniques.