Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.

A method for fabricating a semiconductor device includes: forming an inter-layer dielectric layer and a sacrificial layer over a substrate so that the sacrificial layer covers the inter-layer dielectric layer; forming a conductive pattern that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer; protruding a first portion of the conductive pattern by removing the sacrificial layer while maintaining a second portion of the conductive pattern inside the inter-layer dielectric layer; oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern; removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern; and forming a variable resistance element on top of the conductive pattern to couple a bottom of the variable resistance element with the top of the second portion of the conductive pattern.

Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel; and non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others.

An integrated chip has a memory cell that includes a magnetic tunnel junction (MTJ) device and an access selector apparatus. The MTJ device includes a free layer and a pinned layer. The access selector apparatus includes a first metal structure and a second metal structure separated by one or more non-metallic layers. The first metal structure includes a polarized magnetic layer. The polarized magnetic layer produces a magnetic field that extends through the free layer, tilting its magnetic field and thereby substantially reducing a switching time for the MTJ device. The access selector apparatus may be a bipolar selector. The polarized magnetic layer may be incorporated into an electrode of the bipolar selector. Both the access selector apparatus and the MTJ device may be formed by a stack of material layers. The resulting memory cell may be compact and have good write speed.

According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.

A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

A method according to an exemplary embodiment includes: (a) etching an upper magnetic layer by plasma generated within a processing container, the etching of the upper magnetic layer being terminated on a surface of an insulating layer; (b) removing a deposit formed on a surface of the mask and the upper magnetic layer by etching the upper magnetic layer, by the plasma generated within the processing container; and (c) etching the insulating layer by the plasma generated within the processing container. In the step of removing the deposit, the support structure that holds a processing target is inclined and rotated, and a pulse-modulated DC voltage as a bias voltage for ion attraction is applied to the support structure.

A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.

A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.