An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

According to one embodiment, a magnetic memory device includes a memory cell including a magnetoresistance effect element, a switching element, and a resistance element connected in series. The resistance element has an asymmetric current-voltage characteristic, and when data is read from the memory cell, a first voltage in a reverse direction is applied to the resistance element, and a resistance value of the resistance element at a time when the first voltage is applied is greater than a resistance value of the resistance element at a time when a second voltage in a forward direction having an absolute value identical to an absolute value of the first voltage is applied.

A magnetic memory device includes a three-terminal type memory cell. A first terminal is connected to a first conductor layer. A second terminal is connected to a second conductor layer. A third terminal is connected to a third conductor layer. The memory cell includes a fourth conductor connected to the first conductor layer, the second conductor layer, and the third conductor layer. A magnetoresistance effect element of the memory cell is coupled between the third conductor layer and the fourth conductor layer. A first switching element is coupled to the second conductor layer and the fourth conductor layer. A second switching element coupled to the first conductor layer and the third conductor layer. The fourth conductor layer includes a first ferromagnetic layer and a first non-magnetic layer. The first non-magnetic layer comprises at least one of ruthenium, iridium, rhodium, or osmium.

According to one embodiment, a memory device includes a memory cell including a magnetoresistive effect element. The magnetoresistive effect element includes a non-magnetic layer between first and second electrodes in the first direction, a first magnetic layer between the first electrode and the non-magnetic layer, a second magnetic layer between the second electrode and the non-magnetic layer, and a first layer between the second electrode and the second magnetic layer. The first layer includes oxygen and at least one selected from magnesium, transition metal, and lanthanoid, the first layer has a first size in the first direction, the non-magnetic layer has a second size in the first direction. The first size is 1.1 times or more and 2 times or less the second size.

A semiconductor memory device has a first wiring extending in a first direction and a second wiring extending in a second direction. The first and second wirings are spaced from each other in a third direction. The second wiring has a first recess facing the first wiring. A resistance change memory element is connected between the first and second wirings. A conductive layer is between the resistance change memory element and the second wiring and includes a first protrusion facing the second wiring. A switching portion is between the conductive layer and the second wiring and includes a second recess facing the conductive layer and a second protrusion facing the second wiring. The first protrusion is in the second recess. The second protrusion is in the first recess. The switching portion is configured to switch conductivity state according to voltage between the first wiring and the second wiring.

According to one embodiment, a memory device includes a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a third memory cell adjacent to the first memory cell in a second direction, each of the first, second, and third memory cells including a resistance change memory element and a switching element. The switching element includes first and second electrodes, and a switching material layer between the first and second electrodes, the first and second electrodes overlap each other when viewed from the first direction, the first electrodes in the first and second memory cells are apart from each other, and the switching material layers in the first and second memory cells are continuously provided.

Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

According to one embodiment, a memory device includes: a switching element including first and second conductive layers, and a variable resistive layer between the first and second conductive layers. The first or second conductive layers includes a first layer, a second layer between the first layer and the variable resistive layer, and a third layer between the first layer and the second layer. Each of the first and second layers is selected from a layer including carbon, a layer including nitrogen and carbon, a layer including nitrogen and titanium, a layer including nitrogen and tantalum, a layer including tungsten, a layer including nitrogen and tungsten, and a layer including platinum. The third layer includes at least one selected from lithium, sodium, magnesium, calcium, titanium, or lanthanum.