A variable resistance memory device is provided including a plurality of lower electrodes disposed on a substrate. A plurality of variable resistors are disposed on the plurality of lower electrodes. A plurality of upper electrodes are disposed on the plurality of variable resistors. An interlayer insulating layer fills a space in the plurality of variable resistors. An anti-oxidation layer is disposed between the plurality of variable resistors and the interlayer insulating layer. The anti-oxidation layer covers side surfaces of the plurality of variable resistors, and the anti-oxidation layer comprises silicon and/or carbon.

A magnetoresistive random access memory (MRAM) device and a method of manufacturing the same, the device including a substrate; a memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern on a sidewall of the memory unit; a via on the memory unit and contacting the upper electrode; and a wiring on the via and contacting the via, wherein a center portion of the upper electrode protrudes from a remaining portion of the upper electrode in a vertical direction substantially perpendicular to an upper surface of the substrate.

A magnetoresistive random access memory (MRAM) cell includes a bottom electrode, a magnetic tunnel junction structure, a bipolar tunnel junction selector; and a top electrode. The tunnel junction selector includes a MgO tunnel barrier layer and provides a bipolar function for putting the MTJ structure in parallel or anti-parallel mode.

A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

A memory device may comprise a substrate defining a main plane; a plurality of memory cells each comprising a SOT current layer disposed in the main plane of the substrate and a magnetic tunnel junction residing on the SOT current layer; and a bit line and a source line to flow a write current in a write path including the SOT current layer of a selected memory cell. The source line comprises a conductive magnetic material providing a magnetic bias field extending to the magnetic tunnel junction of the selected memory cell for assisting the switching of the cell state when the write current is flowing.

An example memory includes a plurality of storage units and bit lines distributed in an array in a storage area of the memory, where each of the storage unit includes a transistor and a magnetic tunnel junction (MTJ) element connected to the transistor. The MTJ element is disposed on a current transmission path between a source or a drain of the transistor and the bit line. The MTJ element includes a pinning layer, a reference layer, a tunneling layer, and a free layer that are stacked in sequence, and a magnetization direction of the pinning layer is parallel to a stacking direction of layers in the MTJ. The example memory further includes a first magnetic structure disposed on the current transmission path and in contact with the MTJ element. An included angle between a magnetization direction of the first magnetic structure and the magnetization direction of the pinning layer is (90°, 180°].

A magnetoresistive stack includes a fixed magnetic region, one or more dielectric layers disposed on and in contact with the fixed magnetic region, and a free magnetic region disposed above the one or mom dielectric layers. The fixed magnetic region may include a first ferromagnetic region, a coupling layer, a second ferromagnetic region, a transition layer disposed, a reference layer, and at least one interfacial layer disposed above the second ferromagnetic region. Another interfacial layer may be disposed between the one or more dielectric layers and the free magnetic region.

One illustrative MRAM cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the MTJ element includes a bottom insulation layer positioned above the bottom electrode, a top insulation layer positioned above the bottom electrode; and a first ferromagnetic material layer positioned between the bottom insulation layer and the top insulation layer.

Disclosed is a memory device including a lower electrode, a seed layer, a synthetic antiferromagnetic layer, a magnetic tunnel junction, and an upper electrode laminated on a substrate, wherein the magnetic tunnel junction includes a pinned layer, a tunnel barrier layer, and free layers, wherein the free layers include a first free layer, a spacer layer, a coupling layer, a buffer layer, and a second free layer laminated in sequential order.