A memory device includes; a memory cell array including a first memory cell region and a second memory cell region, a voltage generator configured to generate a code corresponding to a write voltage, and a write driver configured to store data in the first memory cell region in response to the code. The second memory cell region stores a value defining the write voltage, and the write voltage is determined in relation to a reference resistance distinguishing a parallel state and an anti-parallel state for the memory cells, and further in relation to an initial write voltage applied to a magnetic tunnel junction element of at least one of the memory cells.

A method of manufacturing an integrated circuit device comprises forming a layer of barrier material on a surface, where the surface includes interlayer dielectric and a feature of a metal layer. The method may also include forming a layer of contact material above the layer of barrier material. The method may further include removing a portion of the layer of barrier material and a portion of the layer of contact material to form a via. Additionally, the method may include depositing magnetoresistive stack above, and in contact with, the via, where a width of the magnetoresistive stack is greater than or equal to a width of the via.

According to one embodiment, a magnetic memory device includes first to third conductor layers, and a three-terminal-type memory cell connected to the first to third conductor layers. The first memory cell includes a fourth conductor layer, a magnetoresistance effect element, a two-terminal-type first switching element, and a two-terminal-type second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion which is connected to the third conductor layer. The magnetoresistance effect element is connected between the third conductor layer and the fourth conductor layer. The first switching element is connected between the second conductor layer and the fourth conductor layer. The second switching element is connected between the first conductor layer and the third conductor layer.

Data storage devices are provided. A data storage device includes a memory transistor on a substrate and a data storage structure electrically connected to the memory transistor. The data storage structure includes a magnetic tunnel junction pattern and a top electrode on the magnetic tunnel junction pattern. The top electrode includes a first top electrode and a second top electrode on the first top electrode, and the first and second top electrodes include the same metal nitride. The first top electrode includes first crystal grains of the metal nitride, and the second top electrode includes second crystal grains of the metal nitride. In a section of the top electrode, the number of the first crystal grains per a unit length is greater than the number of the second crystal grains per the unit length.

An ultra-fast magnetic random access memory (MRAM) comprises a three terminal bottom-pinned composite SOT magnetic tunneling junction (bCSOT-MTJ) element including (counting from top to bottom) a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer. Such bCSOT-MTJ element will have a very fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.

A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

A magnetoresistive element comprises a nonmagnetic nano-current-channel (NCC) structure provided on a surface of the magnetic recording layer, which is opposite to a surface of the magnetic recording layer where the tunnel barrier layer is provided, and comprising a spatial distribution of perpendicular conducting channels throughout the NCC structure thickness and surrounded by an insulating medium, making the magnetic recording layer a magnetically soft-hard composite structure. Correspondingly, the critical write current and write power are reduced with reversal modes of exchange-spring magnets of the magnetically soft-hard composite structure.

A method for providing a magnetic device and the magnetic device so provided are described. The magnetic device includes a magnetic layer having a surface. In some aspects, the magnetic layer is a free layer, a reference layer, or a top layer thereof. A tunneling barrier layer is deposited on the magnetic layer. At least a portion of the tunneling barrier layer adjacent to the magnetic layer is deposited at a deposition angle of at least thirty degrees from a normal to the surface of the magnetic layer. In some aspects, the deposition angle is at least fifty degrees.