Embodiments provide a layout and a processing method thereof, a storage medium and a program product. The layout has a first memory area and a second memory area. The layout includes a base substrate array pattern and a storage pattern, the base substrate array pattern includes a plurality of plug patterns spaced apart; and the storage pattern includes a magnetic tunnel junction pattern in the first memory area and a capacitor pattern in the second memory area. The magnetic tunnel junction pattern shares a partially overlapped area with a given one of the plurality of plug patterns in the first memory area, and the capacitor pattern shares a partially overlapped area with a given one of the plurality of plug patterns in the second memory area.

A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

A method for fabricating a semiconductor device may include: forming a first magnetic layer over a substrate; forming a tunnel barrier layer over the first magnetic layer by repeatedly performing a unit process of forming a material layer and performing a rapid thermal annealing (RTA) process on the material layer; and forming a second magnetic layer over the tunnel barrier layer.

Double magnetic tunnel junctions and methods of forming the same include a bottom reference layer having a first fixed magnetization and a first thickness. A first tunnel barrier is formed on the bottom reference layer. A free layer is formed on the first tunnel barrier and has a changeable magnetization. A second tunnel barrier is formed on the free layer. A top reference layer is formed on the second tunnel barrier and has a second fixed magnetization that is opposite to the first fixed magnetization and a second thickness that is significantly smaller than the first thickness.

Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit. The storage unit includes a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT, a free layer which includes an elongated member with first and second major surfaces and first and second end regions separated by a free region. The first pinning layer is coupled to the second major surface of the free layer in the first end region and the second pinning layer is coupled to the second major surface of the free layer in the second end region. A reference stack is disposed on the first major surface of the free layer in the free region. The reference stack serves as a read bitline terminal.

In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.

A magnetoresistive element comprises a nonmagnetic sidewall-current-channel (SCC) structure provided on a surface of the SOT material layer that exhibits the Spin Hall Effect, which is opposite to a surface of the SOT material layer where the magnetic recording layer is provided, and comprising an insulating medium in a central region of the SCC structure, and a conductive medium being a sidewall of the SCC structure and surrounding the insulating medium, making an electric current crowding inside the SOT material layer and the magnetic recording layer to achieve a spin-orbit torque and a higher spin-polarization degree for an applied electric current.

A method of making a novel STT-MRAM is disclosed, wherein the STT-MRAM comprises a novel apparatus along with a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory elements having spin-transfer torques acting on a recording layer from a MTJ stack and a novel magnetoresistance with a spin-valve layer. The spin-valve layer is field-reversible between two stable magnetization states either parallel or anti-parallel to the fixed reference layer magnetization through a set/reset current pulse along a conductive line provided by a control circuitry, accordingly, the magetoresistive element is pre-configured into a reading mode having canceled spin-transfer torques or a recording mode having additive spin-transfer torques.

A semiconductor device comprises a first conductive feature on a semiconductor substrate, a bottom electrode on the first conductive feature, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode on the MTJ stack. A spacer contacts a sidewall of the top electrode, a sidewall of the MTJ stack, and a sidewall of the bottom electrode. A conductive feature contacts the top electrode.