A storage element includes a storage layer having a magnetization perpendicular to a layer surface and storing information according to a magnetization state of a magnetic material; a fixed magnetization layer having the magnetization as a reference of the information of the storage layer and perpendicular to the layer surface; an interlayer formed of a nonmagnetic material and interposed between the storage layer and the fixed magnetization layer; a coercive force enhancement layer adjacent to the storage layer, opposite to the interlayer, and formed of Cr, Ru, W, Si, or Mn; and a spin barrier layer formed of an oxide, adjacent to the coercive force enhancement layer, and opposite to the storage layer. The storage layer magnetization is reversed using spin torque magnetization reversal caused by a current in a lamination direction of a layer structure including the storage layer, the interlayer, and the fixed magnetization layer, thereby storing information.

A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.

A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.

An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

The present invention is directed to an MTJ memory element, which comprises a magnetic fixed layer structure formed on top of a seed layer structure that includes a first seed layer and a second seed layer. The first seed layer includes one or more layers of nickel interleaved with one or more layers of a transition metal, which may be tantalum, titanium, or vanadium. The second seed layer is made of an alloy or compound comprising nickel and another transition metal, which may be chromium, tantalum, or titanium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first type material interleaved with layers of a second type material with at least one of the first and second type materials being magnetic. The first and second type materials may be cobalt and nickel, respectively.

A semiconductor device is provided. The semiconductor device includes a first electrode; an MRAM stack formed on the first electrode; a hardmask structure formed on the MRAM stack; a conductive etch stop layer formed around the hardmask structure; and a second electrode formed on the hardmask structure.

The present disclosure provides a semiconductor structure. The semiconductor structure includes an N.sup.th metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M).sup.th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.

Provided is a magnetoresistive effect element having a relatively high magnetoresistance ratio (MR ratio) while reducing element resistance (RA). The magnetoresistive element includes: a first oxide insulating layer provided on one surface side of a magnetization fixed layer; a magnetization free layer provided on the opposite side of the first oxide insulating layer from the magnetization fixed layer side and having perpendicular magnetic anisotropy; a second oxide insulating layer provided on the opposite side of the magnetization free layer from the first oxide insulating layer side; and a metal cap layer provided on the opposite side of the second oxide insulating layer from the magnetization free layer side. The thickness of the second oxide insulating layer is larger than the thickness of the first oxide insulating layer.

This magnetization rotational element includes a spin-orbit torque wiring, and a first ferromagnetic layer in contact with the spin-orbit torque wiring, in which the spin-orbit torque wiring includes a first layer, a second layer, and a third layer in order from a side closer to the first ferromagnetic layer, and a coefficient of linear expansion of a material forming the second layer is between a coefficient of linear expansion of a material forming the first layer and a coefficient of linear expansion of a material forming the third layer.

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.