Semiconductor structure and manufacturing method of the same

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes an N.sup.th metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M).sup.th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.

Claims

1. A semiconductor structure, comprising: an N.sup.th metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region; a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes; a top electrode via over each of the plurality of MTJs; and an (N+M).sup.th metal layer over the plurality of MTJs, wherein N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

2. The semiconductor structure of claim 1, wherein the periphery region occupies more than 90 percent of the semiconductor structure.

3. The semiconductor structure of claim 1, wherein a periphery of the top electrode via is raised to a higher level than a center of the top electrode via.

4. The semiconductor structure of claim 3, further comprising a sidewall spacer laterally contacting the center portion of the top electrode via.

5. The semiconductor structure of claim 3, further comprising an oxide layer surrounding the plurality of MTJs and supporting the periphery of the top electrode via.

6. The semiconductor structure of claim 1, further comprising a planarization etch stop layer over the plurality of MTJs.

7. The semiconductor structure of claim 6, wherein the planarization etch stop layer has a discrete pattern staggering from the plurality of MTJs from a top view perspective.

8. The semiconductor structure of claim 1, wherein the top electrode via comprises a bottom portion at a center, two inclined sidewalls connected to both ends of the bottom portion, and two upper portions connected to the two inclined sidewalls.

9. The semiconductor structure of claim 8, wherein the bottom portion, the two inclined sidewalls, and the two upper portions of the top electrode via form an upward concave shape.

10. The semiconductor structure of claim 6, wherein the planarization etch stop layer is composed of nitride materials or oxynitride materials.

11. A semiconductor structure, comprising: an N.sup.th metal layer in a memory region and a periphery region; a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes; a sidewall spacer layer in the memory region and the periphery region over the plurality of MTJs; an oxide layer in the memory region over the sidewall spacer layer and in the periphery region adjacent to the memory region; and a top electrode via over each of the plurality of MTJs: wherein N is an integer greater than or equal to 1; wherein a periphery portion of the top electrode via is raised to a higher level than a center portion of the top electrode via, and the sidewall spacer layer laterally contacts the center portion of the top electrode via.

12. The semiconductor structure of claim 11, wherein the periphery region occupies more than 90 percent of the semiconductor structure.

13. The semiconductor structure of claim 11, wherein the oxide layer surrounds the plurality of MTJs and supports the periphery portion of the top electrode via.

14. The semiconductor structure of claim 11, further comprising a planarization etch stop layer over the plurality of MTJs.

15. The semiconductor structure of claim 14, wherein the planarization etch stop layer has a discrete pattern staggering from the plurality of MTJs from a top view perspective.

16. The semiconductor structure of claim 11, wherein the top electrode via comprises a bottom portion at a center, two inclined sidewalls connected to both ends of the bottom portion, and two upper portions connected to the two inclined sidewalls.

17. The semiconductor structure of claim 16, wherein the bottom portion, the two inclined sidewalls, and the two upper portions of the top electrode via form an upward concave shape.

18. The semiconductor structure of claim 14, wherein the planarization etch stop layer is composed of nitride materials or oxynitride materials.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

(2) FIG. 1 is a cross section of a semiconductor structure with a mixed sizes MTJ array.

(3) FIG. 2 is a cross section of a semiconductor structure, in accordance with some embodiments of the present disclosure.

(4) FIG. 3 is a top view of a semiconductor structure showing a staggering arrangement of a planarization etch stop pattern with respect to underlying MTJs, in accordance with some embodiments of the present disclosure.

(5) FIG. 4 to FIG. 14 are cross sections of a semiconductor structure fabricated at various stages, in accordance with some embodiments of the present disclosure.

DETAILED DESCRIPTION

(6) The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

(7) Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

(8) Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the term “about” generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term “about” means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the term “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

(9) Embedded MRAM cell in a CMOS structure has been continuously developed. A semiconductor circuit with embedded MRAM cell includes an MRAM cell region and a logic region separated from the MRAM cell region. For example, the MRAM cell region may locate at the center of the aforesaid semiconductor circuit while the logic region may locate at a periphery of the semiconductor circuit. Note the previous statement is not intended to be limiting. Other arrangement regarding the MRAM cell region and the logic region are enclosed in the contemplated scope of the present disclosure.

(10) In the MRAM cell region, a transistor structure can be disposed under the MRAM structure. In some embodiments, the MRAM cell is embedded in the metallization layer prepared in a back-end-of-line (BEOL) operation. For example, the transistor structures in the MRAM cell region and in the logic region are disposed in a common semiconductor substrate, prepared in a front-end-of-line operation, and are substantially identical in the aforesaid two regions in some embodiments.

(11) Conventionally, the MRAM cell is embedded between adjacent metal line layers distributed horizontally parallel to a surface of the semiconductor substrate. For instance, the embedded MRAM can be located between the 4.sup.th metal line layer and the 5.sup.th metal line layer in an MRAM cell region. Horizontally shifted to the logic region, the 4.sup.th metal line layer is connected to the 5.sup.th metal line layer though a 4.sup.th metal via. In other words, taking the MRAM cell region and the logic region into consideration, the embedded MRAM occupies a thickness of at least the 4.sup.th metal via. The number provided for the metal line layer herein is not limiting. In general, people having ordinary skill in the art can understand that the MRAM is located between an N.sup.th metal line layer and an (N+1).sup.th metal line layer, where N is an integer greater than or equal to 1.

(12) The embedded MRAM includes a magnetic tunneling junction (MTJ) composed of ferromagnetic materials. A bottom electrode and a top electrode are electrically coupled to the MTJ for signal/bias conveyance. Following the example previously provided, the bottom electrode is further connected to the N.sup.th metal line layer, whereas the top electrode is further connected to the (N+1).sup.th metal line layer.

(13) Integrated circuit with mixed pitches and/or mixed sizes MTJ array can generate several problems. Conventionally, a backside anti-reflective coating (BARC) is etched back until the exposure of a top electrode of the MTJ. The BARC etch back operation plays an important role in back-end-of-line (BEOL) interconnects in the logic and memory regions. Nevertheless, the BARC etch back encounter various problems when a mixed pitches and/or a mixed sizes MTJ array is to be fabricated. For example, as shown in FIG. 1, a semiconductor structure 10 includes a memory region 100 and a periphery of logic region 110. The memory region 100 includes at least a first size region 100A having a critical dimension CD1 of 70 nanometer and a second size region 100B having a critical dimension CD2 of 100 nanometer. Even if the pitches between adjacent MTJs are fixed in the first size region 100A and the second size region 10011, space between adjacent MTJs with greater critical dimension is narrower than that with smaller critical dimension. Therefore, the oxide layer 121 and the BARC 123 subsequently formed in the space are further piled up in the space between adjacent MTJs in the second size region 100B. When conducting a main etch −Δ during the etch back operation, the oxide layer 121 in the first size region 100A is half-way removed while a top surface of the same in the second size region 100B is just exposed. Moreover, when conducting an over etch −δ during the etch back operation, a spacer layer 124 is exposed in the first size region 100A while the oxide layer 121 in the second size region 100B is just half-way removed. The illustration of FIG. 1 shows the problem of obtaining a uniform BARC etch back result due to the nature of a mixed sizes MTJ array. Similarly, the same problems occur in a mixed pitches MTJ array or a mixed pitches/sizes MTJ array.

(14) The present disclosure provides a manufacturing method achieving a uniform BARC etch back result in a semiconductor structure having a mixed pitches/sizes MTJ array. The semiconductor structure includes a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer. The plurality of MTJs can be arranged in a mixed pitches and/or a mixed sizes fashion. A top electrode via of each of the MTJs appears an upward-concave shape over each MTJs. A planarization etch stop pattern is staggerly disposed over the plurality of MTJs from a top view perspective.

(15) Referring to FIG. 2, FIG. 2 is a cross section of a semiconductor structure 20, in accordance with some embodiments of the present disclosure. The semiconductor structure 20 includes a memory region 200 and a periphery region 210. In some embodiments, the periphery region 210 includes logic components such as a transistor structure. An N.sup.th metal layer 121A′ in the memory region 200 and an N.sup.th metal layer 121B′ in the periphery region 210 are over at least a transistor structure (not shown). In the memory region 200, an MTJ structure 230 is disposed between an Nib metal layer 121A′ and an (N+M).sup.th metal layer 125A′, whereas in the periphery region 210, the Na metal layer 121B′ is connected to the (N+M).sup.th metal layer 125B′. N and M are integers equal to or greater than 1.

(16) In some embodiments, the metal layer referred herein includes metal lines and metal vias composed of copper, gold or another suitable metal or alloy. Metal lines and metal vias in different metal layers form an interconnect structure composed of substantially pure copper (for example, with a weight percentage of copper being greater than about 90 percent, or greater than about 95 percent) or copper alloys, and may be formed using the single and/or dual damascene processes. Metal lines and metal vias may be, or may not be, substantially free from aluminum. Interconnect structure includes a plurality of metal layers, namely M.sub.1, M.sub.2 . . . M.sub.N, Metal layers M.sub.1 through M.sub.N are formed in inter-metal dielectrics (IMDs) 127, which may be formed of oxides such as un-doped Silicate Glass (USG), Fluorinated Silicate Glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials may have k values lower than 3.8, although the dielectric materials of IMDs 127 may also be close to 3.8. In some embodiments, the k values of the low-k dielectric materials are lower than about 3.0, and may be lower than about 2.5. The N.sup.th metal layer 121A′, 121B′ and the (N+1).sup.th metal layer 125A′, 125B′ may be formed by a variety of techniques, e.g., electroplating, electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In some embodiments, the upper metal layer may be (N+M).sup.th metal layer, where M is an integer greater than 1.

(17) In FIG. 2, the plurality of MTJs 230 are positioned over the first metal layer 121A′ in the memory region 200. Although FIG. 2 only illustrates two MTJs 230, various number of MTJs 230 could be adopted as long as the plurality of MTJs includes a mixed sizes and/or a mixed pitches features. By a mixed sizes feature, present disclosure provides at least two different critical dimensions among all the MTJs. By a mixed pitches feature, present disclosure provides at least two different pitches between adjacent MTJs. In some embodiments, only a mixed pitches feature can be observed. In some embodiments, only a mixed sizes feature can be observed. In some embodiments, a mixed pitches feature and a mixed sizes feature can be observed on the semiconductor structure 20. As discussed in FIG. 1, a mixed sizes and/or a mixed pitches MTJ array lead to various space widths in the memory region.

(18) As shown in FIG. 2, a top electrode via 125 is positioned over a top electrode 133 of the MTJ 230. In some embodiments, the top electrode via 125 is in contact with at least the top surface of the top electrode 133 in order to electrically couple to the MTJ 230. In some embodiments, the top electrode via 125 is further in contact with a portion of the sidewall of the top electrode 133 in order to further decrease the resistance. The top electrode via 125 includes a bottom portion, two inclined sidewalls connected to both ends of the bottom portion, and two upper portions connected to the two inclined sidewalls, respectively. As shown in FIG. 2, the MTJ 230 is laterally surrounded by an oxide layer 129, and the two upper portions of the top electrode via 125 are positioned on the top surface of the oxide layer 129. In a top view perspective, a periphery of the top electrode via 125 is supported by the oxide layer 129 and is raised to a higher level than a center of the top electrode via 125. The bottom portion, the two inclined sidewalls, and the two upper portions of the top electrode via 125 form an upward concave shape. Note if the oxide layer 129 is further thinned down to have its top surface lower than the bottom of the top electrode via 125, instead of having an upward concave shape, the top electrode via 125 may appear to have downward concave shape. In this regard, the oxide layer 129 surrounding the MTJs 230 may have a thickness great enough to have its top surface over the bottom of the top electrode via 125.

(19) In FIG. 2, a planarization etch stop layer 201, for example, a chemical mechanical polishing (CMP) stop layer, is positioned over the MTJs 230 and coplanar with the oxide layer 129. The CMP stop layer referred herein indicates an etch stop layer designed for stopping or substantially slow down the CMP operation. As shown in FIG. 2, the planarization etch stop layer 201 possesses a discrete pattern, which means the planarization etch stop layer 201 to the left of one MTJ 230 is not connected to the planarization etch stop layer 201 to the right of the same MTJ 230 in any form From a top view perspective, as illustrated in FIG. 3, the planarization etch stop layer 201 is staggerly arranged over the MTJs 230, which are illustrated in dotted lines, and the planarization etch stop layer 201 forms a discrete pattern array.

(20) Referring to FIG. 3, FIG. 3 is a top view of a semiconductor structure showing a staggering arrangement of a planarization etch stop pattern 300 with respect to underlying MTJs 230A and 230B, in accordance with some embodiments of the present disclosure. As shown in FIG. 3, the planarization etch stop layer 201 are composed of discrete patterns staggerly arranged over the MTJs 230A having a smaller size in a first size area 100A and MTJs 230B having a larger size in a second size area 100B. In some embodiments, a discrete pattern of the planarization etch stop layer 201 can be immediately surrounded by four MTJs 230A from four sides. In other embodiments, a discrete pattern of the planarization etch stop layer 201 can be immediately surrounded by two MTJs 230A from two sides.

(21) The planarization etch stop layer 201 functions as an etch stop to a passivation operation, for example, a chemical mechanical polishing (CMP) operation. The planarization etch stop layer 201 shall possess an etch rate different from that of the oxide layer 129 coplanar therewith. In some embodiments, the planarization etch stop layer 201 can be composed of nitride materials. Alternatively, the planarization etch stop layer 201 can be composed of oxynitride materials.

(22) Referring back to FIG. 2, in some embodiments, the planarization etch stop layer 201 is not laterally overlapped with the periphery of the top electrode via 125. However, in other embodiments, the planarization etch stop layer 201 can be laterally overlapped with the periphery of the top electrode via 125. Note a sidewall spacer 128 is laterally contacting a sidewall of the MTJs 230 and the oxide layer 129. The sidewall spacer 128 is configured to protect the sidewall of the MTJs 230 and expose a portion of the top electrode 133, as previously discussed, for example, a top surface and a portion of the sidewall proximal to the top surface, for electrical coupling to the top electrode via 125.

(23) FIG. 4 to FIG. 14 are cross sections of a semiconductor structure fabricated at various stages, in accordance with some embodiments of the present disclosure. In FIG. 4, a plurality of MTJs 230 are formed over the N.sup.th metal layer 121A′ in the memory region 200. Subsequently, a sidewall spacer 128 is conformably formed over the MTJs 230 and the respective top electrodes 133 in the memory region 200 as well as over the periphery region 210. In some embodiments, the sidewall spacer 128 possesses a thickness of from about 50 Å to about 300 Å, Note a sidewall of the MTJs 230 is surrounded by the sidewall spacer 128 to prevent oxidation or other contamination. Subsequently, an oxide layer 129 is conformably deposited over the sidewall spacer 128 by an atomic layer deposition (ALD) in both the memory region 200 and the periphery region 210. In some embodiments, a plasma-enhanced ALD is adopted to form the oxide layer 129. A thickness of the oxide layer 129 is to be determined according to a level of a top surface thereof relative to the top surface of the top electrode 133. For example, a top surface of the oxide layer 129 at the periphery region 210 is to be greater than or about equal to a top surface of the top electrode 133 of an MTJ 230. As shown in FIG. 4, a top surface of the oxide layer 129 is at least higher than a top surface of the sidewall spacer 128. In some embodiments, present disclosure does not implement any etching operation, selective or non-selective, to the oxide layer 129 so that all the layers subsequently formed follows the contour of the as-deposited oxide layer 129.

(24) In FIG. 5, a sacrificial layer 202 is formed over the oxide layer 129 in the memory region 200 and the periphery region 210. In some embodiments, the sacrificial layer 202 can be formed of an oxide materials, for example, tetraethoxysilane (TEOS), that functions as an etch decelerator in a BARC etch back operation. In some embodiments, a thickness of the oxide layer 129 is substantially similar to that of the planarization etch stop layer 201. Referring to FIG. 6, an ARC 205, or a BARC, is formed over the sacrificial layer 202 with a thickness of more than 800 Angstrom. The flowable nature of ARC 205 mitigates the step heights between the memory region 200 and the periphery region 210, as well as filling the space between adjacent MTJs 230.

(25) In FIG. 7, an ARC 205 etch back operation is performed by an end point detention approach. Because the periphery region 210 spans a significantly wider coverage compare to the memory region 200, in some embodiments the periphery region 210 occupies more than 90 percent of the entire chip area, when the ARC 205 in the periphery region 210 is substantially consumed and the sacrificial layer 202 is exposed, the ARC 205 signal starting to show a decaying trend. At the same time, the ARC 205 in the memory region 200 is not only completely removed, the etch further removes the underlying sacrificial layer 202 and the planarization etch stop layer 201, until the exposure of the oxide layer 129. At the complete of the ARC 205 etch back operation, the oxide layer 129 is exposed in the memory region 200 over each of the plurality of the MTJs 230 while the sacrificial layer 202 still remain in the periphery region 210.

(26) Referring to FIG. 8, a planarization operation is performed over the memory region 200 and the periphery region 210 until the planarization etch stop layer 201 is reached. As previously discussed, because the periphery region 210 occupies significantly greater percentage of the entire chip area compare to the memory region 200, the planarization operation is prone to stop at the level of the planarization etch stop layer 201 in the periphery region 210, rendering complete removal of the sacrificial layer 202 in both regions and a planarized surface having a coplanar oxide layer 129 and a discrete pattern of planarization etch stop layer 201 in the memory region 200, as shown in FIG. 8. In FIG. 8, it should be noted that after the planarization operation, a top surface of the top electrode 133 is not exposed from sidewall spacer 128. Alternatively stated, the top electrode 133 of the MTJ 230 is well protected by the sidewall spacer 128 as well as the oxide layer 129 under the coplanar surface. In order to control the planarization operation to stop at a level higher than the top of the sidewall spacer 128, a top surface of the planarization etch stop layer 201 shall be higher than the top of the sidewall spacer 128 over the top electrode 133.

(27) Referring to FIG. 9, in order to form a top electrode via trench 125′ having a concaving upward shape over each of the MTJs 230, a first photoresist layer 30 is patterned above the memory region 200 and the periphery region 210. Subsequently, an etch operation is performed penetrating through the oxide layer 129 over the memory region 200 until an exposure of the sidewall spacer 128. It should be noted that the top surface of the top electrode 133 is not exposed from sidewall spacer 128 after the etch operation.

(28) Referring to FIG. 10, a lateral etch operation is further performed to remove the sidewall spacer 128 over each of the MTJs 230 within the memory region 200. The etch rate of the sidewall spacer 128 shall be significantly greater than that of the top electrode 133 in the lateral etch operation, thereby the sidewall spacer 128 can partially be removed until an exposure of the sidewall of the top electrode 133 of one of the plurality of MTJs 230 substantially without etching into the top electrode 133. In some embodiments, a portion of the sidewall of the top electrode 133 is exposed after the lateral etch operation. Referring to FIG. 11, a top electrode via layer 125 is deposited over the planarization etch stop layer 201 within both the memory region 200 and the periphery region 210. The top electrode via layer 125 contoured the concaving upward top electrode via trenches 125′, also forming concaving upward shapes. In some embodiments, the top electrode via layer 125 may include titanium (Ti), titanium nitride (TiN), or the like.

(29) Referring to FIG. 12, a second photoresist layer 30′ is patterned over the top electrode via layer 125 above each of the MTJs 230 and inside the contoured top electrode layer trenches 125″ (shown in FIG. 10). The remaining part of the top electrode via layer 125 not covered by the second photoresist layer 30′ is removed. After removing the second photoresist layer 30′, a plurality of top electrode via 125 having concaving upward shapes are exposed. As shown in FIG. 12, the planarization etch stop layer 201 in the periphery region 210 and the memory region 200 is exposed after the patterning of the top electrode via layer 125. The patterned top electrode via layer 125 is in contact with the top surface of at least one of the top electrode 133 in order to electrically couple to the MTJs 230. In some embodiments, the top electrode via 125 is further in contact with a portion of the sidewall of at least one of the top electrode 133 in order to further decrease the resistance. The second photoresist layer 30′ above the MTJs 230 is removed subsequently.

(30) Referring to FIG. 13, the stacks over the periphery region 210, including the planarization etch stop layer 201, the sidewall spacer 128, and the oxide layer 129, are removed. Subsequently, both the memory region 200 and the periphery region 210 are covered by dielectric material. The (N+M).sup.th metal line trenches 1254A within the memory region 200 are formed above the top electrode, as the (N+M).sup.th metal line trenches 125B within the periphery region 210 are formed above the N.sup.th Metal layer 1211B′.

(31) Referring to FIG. 14, a conductive metal is filled into the metal line trenches 125A and 125B, for example, a conventional Dual Damascene operation. The patterned trenches are filled with a conductive material by an electroplating operation, and excess portions of the conductive material are removed from the surface using a chemical mechanical polishing (CMP) operation, an etch operation, or combinations thereof. In some embodiments, the (N+M).sup.th metal layers 125A′ and 125B′ may be formed from copper (Cu), W, AlCu, or the like. In some embodiments, (N+M).sup.th metal layers 125A′ and 125B′ may be formed using the Damascene operation, which should be familiar to those in the art. First, trenches are etched through the dielectric material. This process can be performed by plasma etch operation, such as an Inductively Coupled Plasma (ICP) etch. A dielectric liner (not shown) then may be deposited on the sidewalls of the (N+M).sup.th metal line trenches 125A and 125B. In embodiments, the liner materials may include silicon oxide (SiOx) or silicon nitride (SiNx), which may be formed by plasma deposition process, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) including plasma enhanced chemical vapor deposition (PECVD). Next, a seed layer of Cu is plated in the trenches. Note the seed layer of Cu may be plated over a top surface of the top electrode 133. Then a layer of copper is deposited in the trenches 125A and 125B, followed by planarization of the copper layer, such as by chemical mechanical polishing (CMP), down to the top surface of a dielectric material. The exposed copper surface and dielectric material can be coplanar.

(32) Subsequent processing may further include forming various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate, configured to connect the various features or structures of the integrated circuit device. The additional features may provide electrical interconnection to the device including the formed metal gate structures. For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide. In one example a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure.

(33) Some embodiments of the present disclosure provide a semiconductor structure including a memory region. The memory region includes an N.sup.th metal layer, a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via concaving upward over each of the plurality of MTJs, and an (N+M).sup.th metal layer over the plurality of MTJs. N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

(34) Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (1) forming an N.sup.th metal layer, (2) forming a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, (3) forming a top electrode via concaving upward over each of the plurality of MTJs, and (4) forming an (N+M).sup.th metal layer over the plurality of MTJs. N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

(35) Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes (1) forming an N.sup.th metal layer in a memory region and a periphery region, (2) forming a plurality of magnetic tunneling junctions (MTJs) over the N.sup.th metal layer in the memory region, the plurality of MTJs having at least one of mixed pitches and mixed sizes, (3) forming a top electrode via concaving upward over each of the plurality of MTJs in the memory region, and (4) forming an (N+M).sup.th metal layer in the memory region and the periphery region. N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1.

(36) The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

(37) Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.