Disclosed is a neuromorphic memory element, which includes a first electrode; a second electrode; a first thin film layer adjacent to the first electrode between the first electrode and the second electrode and that is configured to emulate a neuronal plasticity by performing a volatile storage function based on a voltage difference between the first electrode and the second electrode; and a second thin film layer between the first thin film layer and the second electrode and that is configured to emulate a synaptic plasticity by performing a non-volatile storage function.

Disclosed is a neuromorphic memory element, which includes a first electrode; a second electrode; a first thin film layer adjacent to the first electrode between the first electrode and the second electrode and that is configured to emulate a neuronal plasticity by performing a volatile storage function based on a voltage difference between the first electrode and the second electrode; and a second thin film layer between the first thin film layer and the second electrode and that is configured to emulate a synaptic plasticity by performing a non-volatile storage function.

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

A semiconductor device may include: memory cells arranged in a first direction and a second direction intersecting the first direction; first capping patterns extending in the first direction and covering first sidewalls of the memory cells; second capping patterns extending in the second direction and covering second sidewalls of the memory cells; first gap-fill patterns each located between the second capping patterns adjacent in the first direction; second gap-fill patterns each located between the first gap-fill patterns adjacent in the second direction; and barrier layers each located between the second gap-fill patterns.

A semiconductor device may include: memory cells arranged in a first direction and a second direction intersecting the first direction; first capping patterns extending in the first direction and covering first sidewalls of the memory cells; second capping patterns extending in the second direction and covering second sidewalls of the memory cells; first gap-fill patterns each located between the second capping patterns adjacent in the first direction; second gap-fill patterns each located between the first gap-fill patterns adjacent in the second direction; and barrier layers each located between the second gap-fill patterns.

A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.

A memory device includes a memory array structure including a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor, a first peripheral circuit coupled to a first surface of the memory array structure, and a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body.

A memory device includes a memory array structure including a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor, a first peripheral circuit coupled to a first surface of the memory array structure, and a second peripheral circuit coupled to a second surface of the memory array structure opposite to the first surface. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body.

Variable-resistance material memories include a buried salicide word line disposed below a diode. Variable-resistance material memories include a metal spacer spaced apart and next to the diode. Processes include the formation of one of the buried salicide word line and the metal spacer. Devices include the variable-resistance material memories and one of the buried salicided word line and the spacer word line.

A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.