A phase change memory cell including: a first layer in a phase change material; a heating element located under the first layer; a second insulating layer coating a side of the heating element; and a third insulating layer interposed between the first and second layers, in a material having a density higher than that of the material of the second layer.

3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

A phase change material (PCM) memory cell having a metal heater element of sub-EUV dimension. The PCM memory cell includes a bottom electrode of a metal-containing material, a memory cell structure including a phase change material; and a metal heater element of sub-extreme ultraviolet (sub-EUV) dimension situated between and electrically connecting the bottom electrode and PCM memory cell structure. The metal heater element is formed of a circular via structure of sub-EUV dimension and has a seamless metal-nitride fill material. The circular via structure of sub-extreme ultraviolet (sub-EUV) dimension further includes a metal-nitride liner of sub-EUV dimension, the metal-nitride liner of sub-EUV dimension including a thicker metal-nitride liner bottom surface portion and thinner sidewall metal-nitride portions. The thicker metal-nitride liner bottom surface portion improves heat insulation and provides for high resistance/low power switching and reduced amorphous phase change material volumes.

3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth metal layer.

A memory device and method of forming a projection liner under a mushroom phase change memory device with sidewall electrode process scheme to provide self-aligned patterning of resistive projection liner during sidewall electrode formation.

Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.

Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a conductive region; a memory cell including a memory element, a first portion, a second portion, a dielectric portion, and a third portion; and a data line formed over the second and third portions of the memory cell. The memory element is formed over the conductive region. The first portion is formed over the memory element and includes a first conductive material. The second portion is formed over the first portion and includes a second conductive material. The dielectric portion includes a first side adjacent the memory element, the first portion, and the second portion. The third portion includes a third conductive material and is adjacent a second side of the dielectric portion and separated from the memory element, the first portion, and the second portion by the dielectric portion.

A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device includes an active pattern; a gate structure on the active pattern; a bit-line structure electrically connected to the active pattern; a storage node contact electrically connected to the active pattern; and a landing pad electrically connected to the storage node contact, wherein the landing pad includes a first pad flat sidewall and a second pad flat sidewall that are opposite to each other, a third pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a fourth pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a first pad curved sidewall between the first pad flat sidewall and the third pad flat sidewall, and a second pad curved sidewall between the first pad flat sidewall and the fourth pad flat sidewall.

A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device includes an active pattern; a gate structure on the active pattern; a bit-line structure electrically connected to the active pattern; a storage node contact electrically connected to the active pattern; and a landing pad electrically connected to the storage node contact, wherein the landing pad includes a first pad flat sidewall and a second pad flat sidewall that are opposite to each other, a third pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a fourth pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a first pad curved sidewall between the first pad flat sidewall and the third pad flat sidewall, and a second pad curved sidewall between the first pad flat sidewall and the fourth pad flat sidewall.

A phase-change memory device and a method for fabricating the same are provided. The phase-change memory device comprises a first electrode, a stack and a multi-layered spacer. The first electrode is disposed on and electrically connected to an interconnect wiring of the interconnect structure. The stack is disposed on the first electrode and comprises a phase-change layer disposed on the first electrode and a second electrode disposed on the phase-change layer. The multi-layered spacer covers the stack. A first portion of the multi-layered spacer covers a top surface of the stack, and a second portion of the multi-layered spacer covers a sidewall of the stack.