A crystallization seed layer in a substrate, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the crystallization seed layer, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A plurality of memory structures configured in a crossbar array, each including a crystallization seed layer, a phase change material layer above, a top electrode adjacent to a first vertical side surface and a bottom electrode adjacent to a second vertical side surface of the phase change material layer. A method including forming a crystallization seed layer, forming a phase change material layer, forming a top electrode and a bottom electrode on the substrate, each adjacent to a vertical side surface of the phase change material layer.

Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

A memory device comprising a memory array comprising a plurality of memory cells and a metal silicide layer, wherein a memory cell is coupled between a first access line and a second access line and comprises an electrode coupling a storage element to the first access line, wherein the metal silicide layer is between the electrode and the first access line.

According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.

Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.

Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.

Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

A resistive random access memory structure and its manufacturing method are provided. The resistive random access memory structure includes a substrate having an array region and a peripheral region. A first low-k dielectric layer located in the peripheral region has a dielectric constant of less than 3. Memory cells are located on the substrate and in the array region. A dielectric layer covers the memory cells and fills the space between adjacent memory cells in the array region, and its material layer is different from that of the first low-k dielectric layer. First conductive plugs are located in the dielectric layer and each of them is in contact with one of the memory cells. A dummy memory cell is located at the boundary between the array region and the peripheral region, and the dummy memory cell is not in contact with any one of the first conductive plugs.

A signal measuring apparatus comprising: signal circuitry configured to receive an input signal to be measured; and memory circuitry coupled to the signal circuitry and configured to store information representing a magnitude of a voltage or a current of the input signal; wherein the memory circuitry comprises a first memory cell having a material which is arranged to switch from a first material state to a second material state in response to a first switching signal being applied thereto, wherein the first memory cell is tuned to a first value for the first switching signal so that a current or voltage with a magnitude at or above the first value will cause the material of the first memory cell to switch from the first material state to second material state; wherein the apparatus is configured to apply a measurement signal indicative of the input signal to the first memory cell for switching the material of the first memory cell from the first material state to the second material state in dependence on a magnitude of the voltage or current of the measurement signal.