Programmable resistive memory can be integrated with wide-bandgap semiconductor devices on a wide-bandgap semiconductor, silicon, or insulator substrate. The wide-bandgap semiconductor can be group IV-IV, III-V, or II-VI crystal or compound semiconductor, such as silicon carbide or gallium nitride. The programmable resistive memory can be PCRAM, RRAM, MRAM, or OTP. The OTP element can be a metal, silicon, polysilicon, silicided polysilicon, or thermally insulated wide-bandgap semiconductor. The selector in a programmable resistive memory can be a MOS or diode fabricated by wide-bandgap semiconductor.

A non-volatile memory circuit in embodiments of the present invention may have one or more of the following features: (a) a logic source, and (b) a semi-conductive device being electrically coupled to the logic source, having a first terminal, a second terminal and a nano-grease with significantly reduced amount of carbon nanotube loading located between the first and second terminal, wherein the nano-grease exhibits non-volatile memory characteristics.

A non-volatile memory device includes: an insulation layer; a PN diode, which is formed in a monocrystalline silicon layer, a monocrystalline germanium layer or a monocrystalline gallium arsenide layer on the insulation layer; a writing wire which is conductive and is electrically connected to the anode end of the PN diode; a memory unit on the PN diode, the memory unit being electrically connected to a cathode end of the PN diode; and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the PN diode to write the data into the memory unit.

Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.

A semiconductor memory includes: a substrate including a cell region, first and second peripheral circuit regions disposed on two sides of the cell region; first lines extending across the cell region and the first peripheral circuit region; second lines disposed over the first lines and extending across the cell region and the second peripheral circuit region; a contact plug disposed in the second peripheral circuit region and connected to the second line; third lines disposed over the second lines and respectively overlapping the second lines; and first memory cells disposed in the cell region and located at intersections of the first lines and the second lines between the first lines and the second lines, wherein a portion of the third line, located in the cell region contacts the second line, and another portion of the third line located over the contact plug is spaced apart from the second line.

At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes an array overlying a substrate and including multiple memory stacks in a plurality of rows and a plurality of columns. Each of the memory stacks includes a data storage structure having a variable resistance. A plurality of word lines are disposed beneath the array and extend along corresponding rows of the array. The word lines are electrically coupled with memory stacks of the array in the corresponding rows. A plurality of upper conductive vias extend from above the array of memory stacks to contact top surfaces of corresponding word lines.

A memory device may include at least one inert electrode, at least one mask element arranged over the at least one inert electrode, a switching layer arranged over the at least one mask element and the at least one inert electrode, and at least one active electrode arranged over the switching layer. Both of the at least one mask element and the switching layer may be in contact with a top surface of the at least one inert electrode. The switching layer in this memory device may thus include corners at which the conductive filaments may be confined. This memory device may be formed with a process that may utilize the at least one mask element to help reduce the chances of shorting between the inert and active electrodes.

The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

A diode is made of a p-type layer and an n-type layer connected in series between a bottom and top electrode. The p-type and n-type layers have a thickness below 20 nm. A p-type dopant concentration and an n-type dopant concentration are high enough to keep a total resistance across the diode at less than 250Ω when the diode is forward biased while still retaining the characteristics of a diode. In some embodiments, the ratio of an ON current to an OFF current is greater than 2.5×10.sup.4. Alternate embodiments of the diode, arrays of diodes and methods of making diodes are disclosed. Example arrays include memory arrays using diodes and phase change memories (PCMs) connected in series as array elements. The arrays can be stacked in layers and can be made/embodied in the back-end-of-the line (BEOL).