A memory device including a first conductive layer; a second conductive layer; a resistance change region provided between the first conductive layer and the second conductive layer; a first region provided between the resistance change region and the first conductive layer, the first region including a first element selected from the group consisting of niobium, vanadium, tantalum, and titanium, and a second element selected from the group consisting of oxygen, sulfur, selenium, and tellurium, the first region having a first atomic ratio of the first element to the second element; and a second region provided between the first region and the resistance change region, the second region including the first element and the second element, the second region having a second atomic ratio of the first element to the second element, the second atomic ratio being smaller than the first atomic ratio.

A memory includes first lines arrayed along a surface of a substrate. Second lines are arrayed along the surface of the substrate either above or below the first lines and intersecting with the first lines. Resistance change memory cells are provided to correspond to intersection regions between the first lines and the second lines, respectively. First switching elements are arranged on a side of first ends of the first lines and transmitting a first voltage for writing or reading data to at least one memory cell among the memory cells. Second switching elements are arranged on a side of second ends of the first lines on an opposite side to the first ends and transmitting the first voltage to at least another one memory cell among the memory cells. The first switching elements and the second switching elements are connected to different ones of the first lines, respectively.

The array of diodes comprises a matrix plane of diodes arranged according to columns in a first direction and according to rows in a second direction orthogonal to the first direction. The said diodes comprise a cathode region of a first type of conductivity and an anode region of a second type of conductivity, the said cathode and anode regions being superposed and disposed on an insulating layer situated on top of a semiconductor substrate.

Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer; a third level including a second plurality of light emitting diodes (LEDs), the second plurality of LEDs including a third single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.

Techniques for controlling the programming current of a PCM-based AI device using an external resistor are provided. In one aspect, a PCM cell includes: a PCM stack, that has a bottom electrode; a heater disposed directly on the bottom electrode; a PCM unit including a first material disposed on the heater; a top electrode including a second material disposed on the PCM unit; and a resistor adjacent to the PCM stack, wherein the resistor includes a combination of the first material and the second material. A PCM device that includes at least one of the PCM cells, and a method of forming the PCM cell are also provided.

A switching element includes a first conductive layer, a second conductive layer, and a switching material layer provided between the first conductive layer and the second conductive layer and formed of an insulating material containing an additional element. The switching material layer includes a first interface region including a first interface between the first conductive layer and the switching material layer and a second interface region including a second interface between the second conductive layer and the switching material layer. A concentration of the additional element in the switching material layer has a first peak in the first interface region.

A memory cell with a recessed bottom electrode and methods of forming the memory cell are described. A bottom electrode can be deposited on a layer of a structure. A first insulator and a second insulator can be deposited on top of the bottom electrode. The first insulator and the second insulator can be spaced apart from one another to form an opening on top of the bottom electrode. A recess can be etched in the bottom electrode. The recess can be etched in a portion of the bottom electrode that is underneath the opening. The recess and the opening can form a pore. Phase change material can be deposited in the pore to form a memory cell.

According to one embodiment, the semiconductor storage device includes a first wiring extending in a first direction, a second wiring extending in a second direction intersecting the first direction, a first semiconductor device extending in a third direction intersecting the first direction and the second direction, connected to the first wiring and the second wiring, and including a first selector layer and a first variable resistance layer, a first insulator extending in the second and third directions and adjacent to the first semiconductor device in the first direction, and a second insulator extending in the second and third directions and including an air gap disposed between the first semiconductor device and the first insulator.