A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.

A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode disposed over a lower interconnect within a lower inter-level dielectric (ILD) layer over a substrate. A data storage structure is over the bottom electrode. A first top electrode layer is disposed over the data storage structure, and a second top electrode layer is on the first top electrode layer. The second top electrode layer is less susceptible to oxidation than the first top electrode layer. A top electrode via is over and electrically coupled to the second top electrode layer.

Disclosed is a reconfigurable transistor device having a substrate, a plurality of first transistor fingers disposed in a first region over the substrate, and a phase change switch (PCS) having a patch of a phase change material (PCM) disposed over the substrate in a second region to selectively couple a first set of the plurality of first transistor fingers to a bus, wherein the patch of the PCM is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed adjacent to the patch of PCM, wherein the first thermal element is configured to maintain the patch of the PCM to within a first temperature range until the patch of the PCM converts to the amorphous state and maintain the patch of the PCM within a second temperature range until the first patch of PCM converts to the crystalline state.

Resistive random access memory (RRAM) cells, for example conductive bridging random access memory (CBRAM) cells and oxygen vacancy-based RRAM (OxRRAM) cells are provided. An RRAM cell may include a metal-insulator-metal (MIM) structure formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The MIM structure of the RRAM cell may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped insulator in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped insulator. The cup-shaped bottom electrode, or a component thereof (in the case of a multi-layer bottom electrode) may be formed concurrent with interconnect vias, e.g., by deposition of tungsten or other conformal metal.

IC devices with stacked backend memory with resistive switching devices are disclosed. An example IC device includes a support structure, a frontend layer with a plurality of frontend devices, and a backend layer with a plurality of resistive switching devices, the resistive switching devices being, e.g., part of memory cells of stacked backend memory. For example, the backend layer may implement stacked arrays of 1T-1RSD memory cells, with resistive switching devices coupled to some S/D regions of access transistors of the memory cells. Such memory cells may be used to implement stacked eMRAM or eRRAM, with access transistors being TFTs. Stacked TFT-based eMRAM or eRRAM as described herein may help increase density of MRAM or RRAM cells, hide the peripheral circuits that control the memory operation below the memory arrays, and address the scaling challenge of some conventional memory technologies.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an interconnect structure and an electrode layer formed over the interconnect structure. The semiconductor structure also includes a gate dielectric layer formed over the electrode layer and an oxide semiconductor layer formed over the gate dielectric layer. The semiconductor structure also includes an indium-containing feature covering a surface of the oxide semiconductor layer and a source/drain contact formed over the indium-containing feature.

A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.