In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set of bitlines/wordlines of a first layer that traverse row/column termination tiles and main memory tiles adjacent the row/column termination tiles, with each bitline/wordline of the set of bitlines/wordlines connected to another bitline of a second layer in the termination tile.

A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.

A vertical non-volatile memory device may include a plurality of memory cell strings arranged two-dimensionally. Each of the plurality of memory cell strings may include a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of spacers alternately arranged in the first direction and each extending in a second direction, a gate insulating film extending in the first direction and between the channel layer and the plurality of gate electrodes, and a resistance change layer extending in the first direction along a surface of the channel layer. The second direction may cross the first direction. A material in the resistance change layer may be capable of switching between a first state having a first threshold voltage and a second state having a second threshold voltage. The second threshold voltage may be greater than the first threshold voltage.

A memory device and a method for operating a memory device are provided. The memory device includes a stack structure including a memory array stack and a staircase stack, an insulating film on the memory array stack, a conductive film on the staircase stack and on a sidewall of the insulating film, a pillar element on the staircase stack and passing through the conductive film, and memory cells in the memory array stack and electrically connected to the pillar element.

A method for operating a memory device includes following steps. A memory device including a plurality of first electrodes, a plurality of second electrodes and a plurality of memory layers is provided, and a plurality of memory cells are formed at intersections between the first electrodes, the second electrodes and the memory layers. A selected memory cell is selected in the memory cells. V is applied to a selected second electrode in the second electrodes, and the selected second electrode is in electrical contact with the selected memory cell. V is applied to a selected first electrode in the first electrodes, and the selected first electrode is in electrical contact with the selected memory cell. 0 V is applied to unselected second electrodes in the second electrodes. 0 V is applied to unselected first electrodes in the first electrodes.

A memory device includes a first electrode, a second electrode and a memory layer disposed between the first electrode and the second electrode. The memory layer includes a composition including X wt % Cu, Y wt % Ge and Z wt % Se. X ranges between 3.33 and 26.66. Y ranges between 28.33 and 86.66. Z ranges between 10 and 45.

Embodiments provide a semiconductor structure. The semiconductor structure includes a substrate, a dielectric layer arranged on the substrate, and a plurality of memory cell layers. The plurality of memory cell layers are spaced in the dielectric layer along a first direction, and projections of any adjacent two of the plurality of memory cell layers on the substrate are overlapped. Each of the plurality of memory cell layers includes a plurality of memory cells spaced along a second direction. According to the embodiments, the plurality of memory cell layers are spaced in the dielectric layer along a direction perpendicular to the substrate, and each of the plurality of memory cell layers has a plurality of memory cells therein; and a source, a channel and a drain in each of the plurality of memory cells are arranged along a direction parallel to the substrate.

A cross-point memory includes a plurality of memory devices, with each device comprising a memory layer between first and second address lines. In one preferred embodiment, the memory layer comprises an OTS (Ovonic Threshold Switch) film and an antifuse film. In another preferred embodiment, the memory layer comprises an OTS film having a first switch voltage (i.e. forming voltage V.sub.form) greater than all subsequent switch voltages (i.e. threshold voltage V.sub.th). The cross-point memory is preferably a three-dimensional one-time-programmable memory (3D-OTP), including horizontal 3D-OTP and vertical 3D-OTP.