A method for the manufacture of an improved graphene substrate and applications therefor There is provided a method (100) for the manufacture of an electronic device precursor, the method comprising: (i) providing a silicon wafer (200) having a growth surface (205); (ii) forming (105) an insulative layer (210) on the growth surface (205) having a thickness of from 1 nm to 10 nm, preferably 2 nm to 1 nm; (iii) forming (110) a graphene monolayer or multi-layer structure (215) on the insulative layer (210); (iv) optionally forming (115, 120) one or more further layers (220) and/or electrical contacts (225, 230) on the graphene monolayer or multi-layer structure (215); (v) forming (125) a polymer coating (235) over the graphene monolayer or multi-layer structure (215) and any further layers (115) and/or electrical contacts (225, 230); (vi) thinning (130) the silicon wafer (200), or removing the silicon wafer (200) to provide an exposed surface of the insulative layer (210), by etching with an etchant, wherein the silicon wafer (200) is optionally subjected to a grinding step before etching; and (vii) optionally dissolving away (135) the polymer coating (235); wherein the insulative layer (210) and the polymer coating (235) are resistant to etching by the etchant. The resulting conductive graphene substrate can be used in (organic) LEDs, capacitor devices, tunnel FETs and Hall sensors.

Provided are a lateral p-n junction black phosphorus thin film, and a method of manufacturing the same, and specifically, a lateral p-n junction black phosphorus thin film in which a p-type black phosphorus thin film having a p-type semiconductor property and a n-type black phosphorus thin film having a n-type semiconductor property form a lateral junction by modifying some regions on a surface of the black phosphorus thin film through light irradiation with a compound having a specific chemical structure, and a method of manufacturing the same.

An inductive-capacitive (LC) wireless sensor for the detection of toxic heavy metal ions includes inductors and interdigitated electrodes (IDE) in planar form. The sensor is fabricated by screen printing silver (Ag) ink onto a flexible polyethylene-terephthalate (PET) substrate to form a metallization layer. Palladium nanoparticles (Pd NP) is drop casted onto the IDEs to form a sensing layer. The resonant frequency of the LC sensor is remotely monitored by measuring the reflection coefficient (S.sub.11) of a detection coil (planar inductor). The resonant frequency of the LC sensor changes with varying concentrations of heavy metals such as mercury (Hg.sup.2+) and lead (Pb.sup.2+) ions. Changes in the resonant frequency are used to detect the presence and/or concentration of heavy metal ions.

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals) in a pixel or a circuit, the direction of current flowing through the transistor is changed (inverted). That is, by changing the level of voltage applied to a first terminal and a second terminal (terminals serving as a source and a drain) every given period, the source and the drain are switched every given period. Specifically, in a portion which successively outputs signals having certain levels (e.g., L-level signals) in a circuit including a transistor, L-level signals having a plurality of different potentials (L-level signals whose potentials are changed every given period) are used as the signals having certain levels.

The present invention generally relates to nanoscale wires and tissue engineering. Systems and methods are provided in various embodiments for preparing cell scaffolds that can be used for growing cells or tissues, where the cell scaffolds comprise nanoscale wires. In some cases, the nanoscale wires can be connected to electronic circuits extending externally of the cell scaffold. Such cell scaffolds can be used to grow cells or tissues which can be determined and/or controlled at very high resolutions, due to the presence of the nanoscale wires, and such cell scaffolds will find use in a wide variety of novel applications, including applications in tissue engineering, prosthetics, pacemakers, implants, or the like. This approach thus allows for the creation of fundamentally new types of functionalized cells and tissues, due to the high degree of electronic control offered by the nanoscale wires and electronic circuits.

The present disclosure provides a vertical tunneling random access memory comprising: a first electrode disposed on a base substrate; a second electrode vertically spaced from the first electrode; a floating gate disposed between the first electrode and the second electrode and configured to charge or discharge charges; a tunneling insulating layer disposed between the first electrode and the floating gate; a barrier insulating layer disposed between the floating gate and the second electrode; a contact hole passing through the tunneling insulating layer and the barrier insulating layer for partially exposing the first electrode; a semiconductor pattern extending from the second electrode, along and on a portion of a side wall face defining the contact hole, to the first electrode such that one end of the semiconductor pattern is in contact with the first electrode and the other end of the pattern is in contact with the second electrode.

A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.

Processes and formulations for manufacturing a painted circuit are disclosed. In some implementations, a painted circuit can be manufactured using a process including providing a substrate and applying one or more paint layers on a surface of the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers can include a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.

Painted circuit devices, methods, and systems are disclosed. In some implementations, painted circuit devices are created using multiple layers of electrically conductive paint. In one aspect, a painted circuit includes a substrate and one or more paint layer applied to the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers can include a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.