An array substrate includes: a base substrate, a gate line extending in a first direction, a data line extending in a second direction, and a pixel electrode layer, the first direction being substantially perpendicular to the second direction, the gate line and the data line defining a plurality of sub-pixel units, and a plurality of first and second common electrode lines electrically connected to each other and disposed in the same layer as the gate lines. The first common electrode line includes two first common electrode line first portions, and the second common electrode line extends in the second direction. The second common electrode line is located between and electrically connects the two first common electrode line first portions. The second common electrode line is located at a center line of the sub-pixel unit.

Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

The present application provides a pixel structure and an array substrate. The pixel structure includes: a pixel structure, which includes: an electronic switching device; a pixel electrode electrically connected to the electronic switching device, in which the pixel electrode includes a plurality of sub-pixel electrode regions, and the transmittances of the plurality of sub-pixel electrode regions are different; a gate line disposed on a lateral side of the pixel electrode and electrically connected to the electronic switching device; and a data line disposed on another lateral side of the pixel electrode and electrically connected to the electronic switching device.

Provided are a complementary carbon nanotube field effect transistor (CNT-FET) and a manufacturing method thereof. In particular, provided is carbon nanotube-based type conversion technology (p-type.fwdarw.n-type) using a photosensitive polyvinyl alcohol polymer which can be selectively cross-linked at a desired position based on a semiconductor standard process, i.e., photolithography. The CNT-FET includes: a substrate; a first channel layer formed on the substrate and made of a carbon nanotube; a first source electrode formed at one side of the first channel layer and made of a conductive material; a first drain electrode formed at the other side of the first channel layer and made of a conductive material; a conversion induction layer formed on the first channel layer between the first source electrode and the first drain electrode and configured to convert the first channel layer from a p-type to an n-type; a protective layer configured to protect the conversion induction layer; and a first gate electrode formed on the protective layer.

A driving substrate includes a substrate, a plurality of active devices, a thermal-conducting pattern layer and a buffer layer. The active devices are separately arranged on the substrate. Each active device includes a gate, a channel layer, a gate insulation layer, a source and a drain. The source and the drain expose a portion of the channel layer to define a channel region. The thermal-conducting pattern layer is disposed on the substrate and includes at least one thermal-conducting body and at least one thermal-conducting pattern connected to the thermal-conducting body. The thermal-conducting pattern corresponds to a location of at least one of the channel region, the channel layer, the gate, the source and the drain and each active device. The buffer layer is disposed on the substrate and covers the thermal-conducting pattern layer, and is located between the thermal-conducting pattern and each active device.

The present disclosure relates to an organic luminescent substrate. The organic luminescent substrate may include a first organic luminescent field effect transistor and a second organic luminescent field effect transistor. The first organic luminescent field effect transistor may include a first gate electrode, a first electrode, a second electrode, and a first active luminescent layer. The second organic luminescent field effect transistor may include a second gate electrode, a third electrode, a fourth electrode, and a second active luminescent layer. One of the first organic luminescent field effect transistor and the second organic luminescent field effect transistor may be an N-type transistor and the other one may be a P-type transistor. The first gate electrode may be coupled to the second gate electrode.

A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

A flexible display substrate for a foldable display apparatus, a method of manufacturing the flexible display substrate, and a foldable display apparatus are disclosed. The flexible display substrate includes: a first region corresponding to a non-foldable region of the foldable display apparatus; a second region corresponding to a foldable region of the foldable display apparatus; a plurality of first pixel units disposed in the first region, configured to display an image, and each including a polysilicon thin film transistor; and a plurality of second pixel units disposed in the second region, configured to display an image, and each including an organic thin film transistor.

An object of the present invention is to provide an excellent integrated circuit by a simple process. The present invention is an integrated circuit, which includes at least a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory and in which the memory array includes a first semiconductor element having a first semiconductor layer, the rectifying circuit includes a second semiconductor element having a second semiconductor layer, the logic circuit includes a third semiconductor element having a third semiconductor layer, the first semiconductor element is a memory element, the second semiconductor element is a rectifying element, the third semiconductor element is a logic element, the second semiconductor layer is a functional layer exhibiting a rectifying action, the third semiconductor layer is a channel layer of a logic element, and all of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer and all of the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

Apparatus and associated methods related to a three dimensional integrated logic circuit that includes a columnar active region. Within the columnar active region resides an interdigitated plurality of semiconductor columns and conductive columns. A plurality of transistors is vertically arranged along each semiconductor column, which extends from a bottom surface of the columnar logic region to a top surface of the columnar logic region. The plurality of transistors are electrically interconnected so as to perform a logic function and to generate a logic output signal at a logic output port in response to a logic input signal received at a logic input port. Each of the plurality of conductive columns is adjacent to at least one of the plurality of semiconductor columns and extends along a columnar axis to one or more interconnection layers at the top and/or bottom surfaces of the columnar active layer.