In a method of forming a gate-all-around field effect transistor (GAA FET), a bottom support layer is formed over a substrate and a first group of carbon nanotubes (CNTs) are disposed over the bottom support layer. A first support layer is formed over the first group of CNTs and the bottom support layer such that the first group of CNTs are embedded in the first support layer. A second group of carbon nanotubes (CNTs) are disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer such that the second group of CNTs are embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer.

Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

A thin film transistor includes a gate electrode, an insulation film disposed on the gate electrode, a semiconductor layer facing the gate electrode with the insulation film in between, and a source-drain wiring layer electrically coupled to the semiconductor layer, and including a first wiring layer and a second wiring layer. The first wiring layer is in contact with the semiconductor layer between the semiconductor layer and the insulation film, and is configured of a transparent electroconductive film. The second wiring layer is overlapped with a portion of the first wiring layer. Another semiconductor layer made of a material same as a material of the semiconductor layer is stacked on the second wiring layer.

An organic thin film transistor includes a drain electrode, a semiconductor layer, a source electrode, a gate insulator, and a gate electrode. A horizontal portion and a vertical portion of the semiconductor layer are respectively located on a top surface and an end surface of the drain electrode, and the drain electrode protrudes from the horizontal portion in a first direction. The source electrode is disposed along a surface of the semiconductor layer. The source electrode has an extending portion that extends in a second direction opposite to the first direction. The gate insulator is disposed along a top surface and two side surfaces of a stacked structure defined by the drain electrode, the semiconductor layer, and the source electrode. The gate electrode is located on the gate insulator, and a portion of the gate insulator is between the stacked structure and the gate electrode.

Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

A ratiometric vapor sensor is described that includes a first sensor and a second sensor. The first sensor includes a first semiconductor component comprising a vapor-sensitive semiconducting organic compound, while the second sensor includes a second semiconductor component comprising a modified vapor-sensitive semiconducting organic compound including a modifying organic group. The ratiometric vapor sensor can be used to detect the presence of a vapor such as nitrogen dioxide, and determine the concentration of the vapor by comparing the outputs of electrodes connected to the first and second sensor.

Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other. Thereby, the static RAM core cell is configured such that organic transistors of the same type are arranged in the same plane and are vertically stacked, thus omitting a complicated patterning process for forming organic transistors of different types upon fabrication of a memory element, and also reducing the area occupied by the memory element to thereby increase the degree of integration of semiconductor circuits.

The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

Methods for producing and integrating single-walled carbon nanotubes (SWCNT) into existing TFT backplane manufacturing lines are provided. In contrast to LTPS and oxide TFT backplanes, SWCNT TFT backplanes exhibit either equivalent or better figures of merit such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and low power, bendability and low cost. Methods and processes for integrating SWCNTs technologies into existing TFT backplane manufacturing lines, pilot test and mass production can start without additional capex needs are also provided.

In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.