Embodiments of the present disclosure provide a display panel, a method of manufacturing the display panel, a fingerprint identification device, and a method of identifying a fingerprint. The display panel includes first and second substrates. The first substrate is formed with switch transistors arranged in an array, and photosensitive elements arranged in an array and connected with the switch transistors. The second substrate is formed with conductive contact members, the contact members each have an end adjacent to the first substrate, and the end of each of the contact members is spaced from the first substrate so that when the second substrate is deformed by a force, the end of at least one of the contact members electrically contacts the first substrate so that at least one of the switch transistors in a position corresponding to the at least one of the contact members is turned on.

A vertical field-effect transistor is provided, comprising a first electrode, a porous conductor layer formed from a layer of conductive material with a plurality of holes extending through the conductive material disposed therein, a dielectric layer between the first electrode and the porous conductor layer, a charge transport layer in contact with the porous conductor layer, and a second electrode electrically connected to the charge transport layer. A photoactive layer may be provided between the dielectric layer and the first electrode. A method of manufacturing a vertical field-effect transistor may also be provided, comprising forming a dielectric layer and depositing a conductor layer in contact with the dielectric layer, wherein one or more regions of the dielectric layer are masked during deposition such that the conductor layer includes a plurality of pores that extend through the conductor layer.

Methods for producing and integrating single-walled carbon nanotubes (SWCNT) into existing TFT backplane manufacturing lines are provided. In contrast to LTPS and oxide TFT backplanes, SWCNT TFT backplanes exhibit either equivalent or better figures of merit such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and low power, bendability and low cost. Methods and processes for integrating SWCNTs technologies into existing TFT backplane manufacturing lines, pilot test and mass production can start without additional capex needs are also provided.

A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion.

A system that includes an energy device having an active region configured to generate or consume electrical energy provided by an electrical current is discussed. A current limiter is disposed between the energy device and a current collector layer. The current limiter controls the current flow between the energy device and the current collector layer. A plurality of electrochemical transistors (ECTs) are arranged in an array such that each ECT in the array provides localized current control for the energy device. Each ECT includes a gate electrode, a drain electrode, a source electrode, and a channel disposed between the drain and the source electrodes. An electrolyte electrically couples the gate electrode to the channel such that an electrical signal at the gate electrode controls electrical conductivity of the channel. The current collector layer is a shared drain or source electrode for the ECTs.

An excellent complementary semiconductor device is provided using a simple process. An n-type drive semiconductor device including a substrate; and a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and including a second insulating layer on the opposite side of the semiconductor layer from the gate insulating layer; in which the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom; and in which the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof.

An object of the present invention is to provide a ferroelectric memory element which has a low driving voltage and which can be formed by coating. The present invention provides a ferroelectric memory element including at least: a first conductive film; a second conductive film; and a ferroelectric layer provided between the first conductive film and the second conductive film; wherein the ferroelectric layer contains ferroelectric particles and an organic component, and wherein the ferroelectric particles have an average particle size of from 30 to 500 nm.

Van der Waals heterojunctions are extended to semiconducting p-type single-walled carbon nanotube (s-SWCNT) and n-type film that can be solution-processed with high spatial uniformity at the wafer scale. The resulting large-area, low-voltage p-n heterojunctions can exhibit anti-ambipolar transfer characteristics with high on/off ratios. The charge transport can be efficiently utilized in analog circuits such as frequency doublers and keying circuits that are widely used, for example, in telecommunication and wireless data transmission technologies.

A method of forming a stack of layers defining one or more electronic devices, the method comprising: depositing a first thickness of curable, dielectric or dielectric precursor material over an area of a workpiece; thereafter exposing the workpiece to curing conditions at least over said area of said workpiece; and without any intermediate patterning operation, thereafter depositing a second thickness of said curable material over said area of said workpiece; and thereafter again exposing the workpiece to curing conditions at least over said area of said workpiece.

Processes and formulations for manufacturing a painted circuit are disclosed. In some implementations, a painted circuit can be manufactured using a process including providing a substrate and applying one or more paint layers on a surface of the substrate, where the one or more paint layers each form an electrical component of the painted circuit. A given paint layer of the one or more paint layers can include a conductive paint formulation having a resistance that is defined by a concentration of conductive material that is included in the conductive paint formulation and a thickness of the given paint layer, and lower concentrations of the conductive material included in the conductive paint formulation provide a higher resistance than higher concentrations of conductive material.