The present invention provides a bio-sensing device. The bio-sensing device includes an array of unit cells, each unit cell including: a source electrode and a drain electrode spaced apart from each other; a sensing film that serves as a channel between the source electrode and the drain electrode; and gate electrodes spaced apart from the sensing film, wherein the gate electrodes is disposed at a lower level than the source electrode, the drain electrode and the sensing film.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

We describe a method for reducing a parasitic resistance at an interface between a conducting electrode region and an organic semiconductor in a thin film transistor, the method comprising: providing a solution comprising a dopant for doping said semiconductor, and depositing said solution onto said semiconductor and/or said conducting electrode region to selectively dope said semiconductor adjacent said interface between said conducting electrode region and said semiconductor, wherein depositing said solution comprises inkjet-printing said solution.

A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes.

A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

An active matrix light emitting diodes display module integrated with single-walled carbon nanotubes control circuits includes a light emitting diode pixel having a crystalline semiconductor light emitting diode, single-walled carbon nanotubes switching transistors and a charge storage capacitor.

A method for fabricating at least a portion of a complementary circuit, such as a complementary inverter circuit, includes fabricating a first sheet and a second sheet. Each of the sheets includes metal layers, a dielectric layer, and a semiconductor channel layer, configured so as to form a plurality of transistors of a respective polarity (i.e., P-type for one sheet, N-type for the other). The method also includes placing a layer of conductive material, such as anisotropic conducting glue (ACG) or anisotropic conducting foil (ACF), on the first sheet, and bonding at least a portion of the second sheet to the first sheet such that the conductive material is disposed between and in contact with the top-most metal layers of the first and second sheets. Separately fabricating the two sheets of different polarity may improve yields and/or decrease costs as compared to fabricating both polarities on a single substrate.

To provide an inspection device and an inspection method which are capable of detecting a disconnection defect in an organic TFT array and/or evaluating a variation in the output properties and response speed of each organic TFT element. There are provided a device and a method of optically measuring the presence or absence of the accumulation of carriers in an organic semiconductor thin film which provides a channel layer of an organic TFT element. A source and a drain in each organic TFT are short-circuited to each other, a voltage is turned on and turned off in a predetermined period between this and a gate, and images before and after application of the voltage are captured in synchronization with the predetermined period while radiating monochromatic light, to obtain a differential image.

The present invention proposes an array substrate and a method for fabricating the same. According to the array substrate and the method of fabricating the array substrate in the present invention, the IGZO pattern and the first electrode strip, the first channel, and the second metallic layer in the corresponding section form the first transistor of the CMOS inverter, and the OSC pattern and the second electrode strip, the second channel, and the second metallic layer in the corresponding section form the second transistor of the CMOS inverter. In this way, the CMOS inverter or the CMOS ring oscillator is fabricated based on IGZO and OSC.

A thin film transistor includes a gate electrode, an insulating layer disposed on the gate electrode, and an active layer disposed on the insulating layer, where the active layer includes a perovskite compound represented by the following Formula: AB.sub.(1-u)C.sub.(u)[X.sub.(1-v)Y.sub.(v)].sub.3, where A is a monovalent organic cation, a monovalent inorganic cation, or any combination thereof, B is Sn.sup.2+, C is a divalent cation or trivalent cation, X is a monovalent anion, Y is a monovalent anion different from X, u is a real number greater than 0 and less than 1, and v is a real number greater than 0 and less than 1.