A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.

Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.

The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

A two-bit memory device having a layer structure containing in order a bottom layer, a molecular layer containing a chiral compound having at least one polar functional group, and a top layer, which is electrically conductive and ferromagnetic. The chiral compound acts as a spin filter for electrons passing through the molecular layer. The chiral compound is of flexible conformation and has a conformation-flexible molecular dipole moment. An electrical resistance of the layer structure for an electrical current running from the bottom layer to the top layer has at least four distinct states which depend on the magnetization of the top layer and on the orientation of the conformation-flexible dipole moment of the chiral compound. Furthermore, a method for operating the two-bit memory device and an electronic component containing at least one two-bit memory device.

The invention relates to a process for the production of an electronic component comprising a self-assembled monolayer (SAM) using compounds of the formula I
R.sup.1-(A.sup.1-Z.sup.1).sub.r(B.sup.1).sub.n(Z.sup.2-A.sup.2).sub.s-Sp-G(I)
in which the groups occurring have the meanings defined in Claim 1; the present invention furthermore relates to the use of the components in electronic switching elements and to compounds for the production of the SAM.

An electronic component such as a voltage controllable reconfigurable capacitor or transistor is formed by printing one or more layers of ink on a non-conductive substrate. Ferroelectric ink or semi-conductive ink is printed and conductive resistive or dielectric ink is printed on a s same or different layers. Reconfigurability is achieved by printing resistive biasing circuitry wherein when a changing voltage is applied to the biasing circuitry, an electronic property of the electronic component changes in response to the changing voltage.

A method for producing a memory cell includes providing a non-conductive substrate, mounting a first conductor track made of conductive material on the non-conductive substrate, mounting a porous dielectric with or without redox-active molecules in a form of points on the first conductor track, and mounting a second conductor track orthogonally to the first conductor track, wherein the first and second conductor tracks have an electrode function at their intersection point, and wherein the porous dielectric is arranged between the electrodes. The method further includes mounting a passivation layer on the substrate, the first conductor track, the dielectric, and the second conductor track, so that the conductor track remains contactable. The first and the second conductor track form a memory at their intersection point with the dielectric arranged between them, in which the redox reaction of the redox-active molecules is configured to be driven by a voltage.

The invention relates to a ferroelectric memory device comprising at least one layer comprising a ferroelectric polymer, and at least two electrodes either side thereof, the ferroelectric polymer being of general formula P(VDF-X-Y), wherein VDF is vinylidene fluoride motifs, X is trifluoroethylene or tetrafluoroethylene motifs, and Y is motifs from a third monomer, the molar proportion of Y motifs in the polymer being less than or equal to 6.5%.

An improved switching material for forming a composite article over a substrate is disclosed. A first volume of nanotubes is combined with a second volume of nanoscopic particles in a predefined ration relative to the first volume of nanotubes to form a mixture. This mixture can then be deposited over a substrate as a relatively thick composite article via a spin coating process. The composite article may possess improved switching properties over that of a nanotube-only switching article. A method for forming substantially uniform nanoscopic particles of carbon, which contains one or more allotropes of carbon, is also disclosed.

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.