H10K19/202

Combinational Resistive Change Elements
20200388331 · 2020-12-10 · ·

The present disclosure generally relates to combinations of resistive change elements and resistive change element arrays thereof. The present disclosure also generally relates to combinational resistive change elements and combinational resistive change element arrays thereof. The present disclosure additionally generally relates to devices and methods for programming and accessing combinations of resistive change elements. The present disclosure further generally relates to devices and methods for programming and accessing combinational resistive change elements.

Method for producing a memory cell having a porous dielectric and use of the memory cell

A method for producing a memory cell includes providing a non-conductive substrate, mounting a first conductor track made of conductive material on the non-conductive substrate, mounting a porous dielectric with or without redox-active molecules in a form of points on the first conductor track, and mounting a second conductor track orthogonally to the first conductor track, wherein the first and second conductor tracks have an electrode function at their intersection point, and wherein the porous dielectric is arranged between the electrodes. The method further includes mounting a passivation layer on the substrate, the first conductor track, the dielectric, and the second conductor track, so that the conductor track remains contactable. The first and the second conductor track form a memory at their intersection point with the dielectric arranged between them, in which the redox reaction of the redox-active molecules is configured to be driven by a voltage.

Cross-point array of polymer junctions with individually-programmed conductances that can be reset

Memory devices are provided having a cross-point array of polymer junctions with individually-programmed conductances that can be reset. In one aspect, a memory device is provided. The memory device includes: bottom metal lines; top metal lines; and polymer junctions in between the bottom metal lines and the top metal lines, wherein the polymer junctions include an organic polymer doped with a spiropyran and an acid. A method of forming and a method of operating the memory device are also provided.

Electron transport gate circuits and methods of manufacture, operation and use
10817780 · 2020-10-27 ·

A circuit is disclosed that includes a first electrode, a second electrode and a plurality of quantum dot devices disposed between the first electrode and the second electrode. An impedance is coupled to the second electrode and has a value selected to conduct or block conduction of current when a coherent electron conduction band is formed by one or more of the quantum dot devices, such as with quantum dot devices in an adjacent circuit.

Printed reconfigurable electronic circuit

An electronic component such as a voltage controllable reconfigurable capacitor or transistor is formed by printing one or more layers of ink on a non-conductive substrate. Ferroelectric ink or semi-conductive ink is printed and conductive resistive or dielectric ink is printed on a s same or different layers. Reconfigurability is achieved by printing resistive biasing circuitry wherein when a changing voltage is applied to the biasing circuitry, an electronic property of the electronic component changes in response to the changing voltage.

Machine Learning Processor Employing a Monolithically Integrated Memory System
20200307995 · 2020-10-01 ·

Disclosed are systems and methods for monolithically-integrating an artificial intelligence processor system and a nanotube memory system on the same die to achieve high memory density and low power consumption.

Three Dimensional (3D) Memories with Multiple Resistive Change Elements per Cell and Corresponding Architectures for In-Memory Computing
20240013834 · 2024-01-11 · ·

The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell. Isolating each multi-switch storage cell in a three-dimensional MSSC array, enables in-memory computing for applications such as data processing for machine learning and artificial intelligence.

Array substrate, manufacturing method thereof and display device

An array substrate, manufacturing method thereof, and display device are disclosed. The array substrate includes signal lines; IC connection lines; the IC connection lines include at least two IC connection line groups, the at least two IC connection line groups comprise a first IC connection line group and a second IC connection line group, the array substrate further includes a lead, an orthographic projection of the lead on a straight line in a second direction is overlapped or connected with an orthographic projection of a first IC connection line in the first IC connection line group which is closest to the second IC connection line group on the straight line in a second direction and an orthographic projection of the second IC connection line in the second IC connection line group which is closest to the first IC connection line group on the straight line in a second direction respectively.

Josephson Toroidal Vortex Quantum Superconductive/Memcapacitive and Superconductive/Memristive Devices of Making and Their Applications at Room Temperature Thereto
20200264130 · 2020-08-20 ·

Multiple Josephson toroidal vertex quantum superconductive/memristive and superconductive/memcapacitive devices were invented with various superlattice structures, which work at room temperature without an applied external magnetic flux. The first type of the superlattices of the devices comprises of multiple-layers of organometallic polymers on gold chips by self-assembling that mimics the function of Matrix Metalloproteinase-2 (MMP-2). Another type of quantum superconductor/memristor comprises of multiple-organic polymers cross-linked with MMP-2 protein forming Josephson toroidal vertex on the gold surface. Models of the quantum superconductive/memristive and superconductive/memcapacitive devices were fabricated in nano superlattice structures and the devices module configurations were described. Three different methods were used to evaluate the devices' applications in sub fg/mL collagen-1 sensing, energy storage, and the super-position characteristics as a potential quantum bit device. The superconductivity, memristive, and memcapacitive functions were also evaluated in multiple methods, respectively.

Electronic component including molecular layer

An electronic component (10) comprising a plurality of switching elements (1) which comprise, in this sequence, a first electrode (16), a molecular layer (18) bonded to a substrate, and a second electrode (20), where the molecular layer essentially consists of molecules (M) which contain a connecting group (V) and an end group (E) having a polar or ionic function, is suitable as memristive device for digital information storage.