The invention comprises a method of forming a magnetic free layer having a (100) texture and a novel magnetic pinning structure having a (100) textured or cube-textured reference layer through a non-epitaxial texturing approach so that an excellent coherent tunneling effect is achieved in a pMTJ element due to its texture structure of Fe or CoFe BCC (100)/MgO rocksalt (100)/Fe or CoFe BCC (100). The invention also discloses a pMTJ element comprising a soft-magnetic adjacent layer having at least one high-permeability material layer having a near-zero magnetostriction. Correspondingly, a high MR ratio and a coherent domain reversal of the magnetic free layer can be achieved for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

A memory device is provided, the memory device comprising a contact pillar in a dielectric layer. A magnetic tunnel junction may be provided over the contact pillar. A barrier layer may be provided on a sidewall of the magnetic tunnel junction and extending over a horizontal surface of the dielectric layer. A spacer may be provided over the barrier layer.

There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film.

A memory slot including a pad formed of a stack of regions made of thin layers, including a first region made of a nonmagnetic conducting material; a second region made of a magnetic material exhibiting a magnetization in a direction perpendicular to the principal plane of the pad; a third region made of a nonmagnetic conducting material of different characteristics to those of the first region; the pad resting on a conducting track adapted to cause the flow of a programming current of chosen sense, in which the pad has an asymmetric shape with respect to any plane perpendicular to the plane of the layers and parallel to the central axis of the track, and with respect to its barycenter.

The present invention relates to a sensor device which has high S/N and excellent temperature characteristics. A sensor device has a semiconductor substrate, a first metal wiring layer provided on the semiconductor substrate, a first insulating layer provided on the first metal wiring layer, a compound semiconductor sensor element provided on the first insulating layer, a second metal wiring layer provided on the compound semiconductor sensor element and the first insulating layer, and a second insulating layer provided on the second metal wiring layer. A third insulating layer is provided between the first metal wiring layer and the second metal wiring layer, and the compound semiconductor sensor element is provided in the third insulating layer.

According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.

An improved magnetic tunnel junction with two oxide interfaces on each side of a ferromagnetic layer (FML) leads to higher PMA in the FML. The novel stack structure allows improved control during oxidation of the top oxide layer. This is achieved by the use of a FML with a multiplicity of ferromagnetic sub-layers deposited in alternating sequence with one or more non-magnetic layers. The use of non-magnetic layers each with a thickness of 0.5 to 10 Angstroms and with a high resputtering rate provides a smoother FML top surface, inhibits crystallization of the FML sub-layers, and reacts with oxygen to prevent detrimental oxidation of the adjoining ferromagnetic sub-layers. The FML can function as a free or reference layer in an MTJ. In an alternative embodiment, the non-magnetic material such as Mg, Al, Si, Ca, Sr, Ba, and B is embedded by co-deposition or doped in the FML layer.

An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.

According to one embodiment, a semiconductor storage device includes a memory cell, a bit line connected to the memory cell, and a sense circuit connected to the bit line, wherein the sense circuit includes a first transistor with a first end connected to the bit line, a second transistor with a first end connected to a second end of the first transistor, a third transistor with a first end connected to the bit line, a fourth transistor with a first end connected to a second end of the third transistor, and an amplifier connected to a second end of the second transistor and to a second end of the fourth transistor.

Synthesizing a control object for a computing event, the control object for securing a computing resource based on a set of access and privilege information provided through a set of mediated associations that are represented by an enchained set of certificates, portions of which are encrypted including entity-specific paths to entity-specific predecessor certificates and partial decryption keys therefor, wherein the control object is applied to secure the computing resource for performing a computing action indicated by a process-type entity identified in the certificate for the control object.