An SOT-driven field-free switching MRAM and an array thereof. From top to bottom, the SOT-MRAM sequentially includes: a selector (1) configured to turn on or turn off the SOT-MRAM under an action of an external voltage; a magnetic tunnel junction (2), including a ferromagnetic reference layer, a tunneling layer and a ferromagnetic free layer arranged sequentially from top to bottom; and a spin-orbit coupling layer (3) made of one or more selected from heavy metal, doped heavy metal, heavy metal alloy, metal oxide, dual heavy metal layers, semiconductor material, two-dimensional semi-metal material and anti-ferromagnetic material. The spin-orbit coupling layer is configured to generate an in-plane effective field in the ferromagnetic free layer by using the interlayer exchange coupling effect and generate spin-orbit torques by using the spin Hall effect, so as to perform a deterministic data storage in the magnetic tunnel junction (2).

A spin-selective conduction structure comprises a crystal having a monolayer of metal atoms between two layers of chiral organic molecules. Each metal atom is coupled to two chiral organic molecules, one at each layer, wherein a chirality of organic molecules in one of the two layers is the same as a chirality of organic molecules in another one of the two layers.

A spin-selective conduction structure comprises a crystal having a monolayer of metal atoms between two layers of chiral organic molecules. Each metal atom is coupled to two chiral organic molecules, one at each layer, wherein a chirality of organic molecules in one of the two layers is the same as a chirality of organic molecules in another one of the two layers.

In one embodiment, a first integrated circuit component, a second integrated circuit component, and an electrical interconnect coupling the first integrated circuit component and the second integrated circuit component. The interconnect comprises one or more spintronic logic devices.

A method for measuring the intensity of an external magnetic field by using a magnetic memory point including a storage layer having a magnetisation switchable between two magnetisation directions substantially perpendicular to the plane of the layer; a reference layer having a fixed magnetisation perpendicular to the plane of the layer; and a tunnel barrier layer separating the storage layer and the reference layer; the method including successively applying a plurality of currents or voltages of different amplitudes to the memory point until switching of the magnetisation direction of the storage layer takes place to determine a minimum switching current value of the magnetisation direction of the storage layer or a minimum switching voltage value of the magnetisation direction of the storage layer, and determining the intensity of the external magnetic field to be measured from the minimum switching current value or the minimum switching voltage value.

There is provided a method of manufacturing a magnetoresistive element. The method comprises: (a) placing a substrate on a substrate support of an oxidation processing apparatus, the substrate having a ferromagnetic layer and a magnesium layer provided on the ferromagnetic layer; and (b) oxidizing the magnesium layer by supplying oxygen gas to the substrate in a state where a temperature of the substrate support is set to 150 Kelvin or less to form a magnesium oxide layer from the magnesium layer.

There is provided a method of manufacturing a magnetoresistive element. The method comprises: (a) placing a substrate on a substrate support of an oxidation processing apparatus, the substrate having a ferromagnetic layer and a magnesium layer provided on the ferromagnetic layer; and (b) oxidizing the magnesium layer by supplying oxygen gas to the substrate in a state where a temperature of the substrate support is set to 150 Kelvin or less to form a magnesium oxide layer from the magnesium layer.

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

Voltage-controlled spin field effect transistors (“spin transistors”) and methods for their use in switching applications are provided. In the spin transistors, spin current is transported from a spin injection contact to a spin detection contact through a multiferroic antiferromagnetic channel via magnon propagation. The spin current transport is modulated by the application of a gate voltage that increases the number of domain boundaries the multiferroic antiferromagnetic material.

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals, where the active region includes a source, a drain, and a channel region; a word line, where the word line is connected to the channel region and extends along a first direction; a bit line, where the bit line is connected to the drain or the source and extends along a second direction, the first direction being different from the second direction; and a magnetic memory cell, connected to the source or the drain.