A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.

A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

A device including a multi-layered structure that includes: a first layer that includes a first magnetic Heusler compound; a second layer that is non-magnetic at room temperature and includes both Ru and at least one other element E, wherein the composition of the second layer is represented by Ru1−xEx, with x being in the range from 0.45 to 0.55; and a third layer including a second magnetic Heusler compound. The multi-layered structure may overlay a substrate. The device may include a tunnel barrier overlying the multi-layered structure.

A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.

A semiconductor device for internet of things (IoT) device includes a substrate having an array region defined thereon and a ring of dummy pattern surrounding the array region. Preferably, the ring of dummy pattern includes a plurality of magnetic tunneling junctions (MTJs) and a ring of metal interconnect pattern overlapping the MTJs and surrounding the array region. The semiconductor device further includes a gap between the array region and the ring of dummy pattern.

Provided are a magnetic tunneling junction device having a relatively high tunneling magnetoresistance (TMR) ratio; and a memory device including the magnetic tunneling junction device. The magnetic tunneling junction device includes: a pinned layer having a first surface and a second surface opposite the first surface; a seed layer disposed in contact with the first surface of the pinned layer; a free layer disposed to face the second surface of the pinned layer; and a tunnel barrier layer disposed between the pinned layer and the free layer, wherein the seed layer includes at least one amorphous material selected from CoFeX and CoFeXTa, and the X includes at least one element selected from niobium (Nb), molybdenum (Mo), tungsten (W), chromium (Cr), zirconium (Zr), and hafnium (Hf). The seed layer may not include boron.

Provided are a magnetic tunneling junction device having a relatively high tunneling magnetoresistance (TMR) ratio; and a memory device including the magnetic tunneling junction device. The magnetic tunneling junction device includes: a pinned layer having a first surface and a second surface opposite the first surface; a seed layer disposed in contact with the first surface of the pinned layer; a free layer disposed to face the second surface of the pinned layer; and a tunnel barrier layer disposed between the pinned layer and the free layer, wherein the seed layer includes at least one amorphous material selected from CoFeX and CoFeXTa, and the X includes at least one element selected from niobium (Nb), molybdenum (Mo), tungsten (W), chromium (Cr), zirconium (Zr), and hafnium (Hf). The seed layer may not include boron.

An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.

A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.