Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a spin transfer torque (STT) magnetoresistive random access memory (MRAM) stack. The semiconductor structure may also include a spin orbit torque (SOT) MRAM stack vertically in series with the STT-MRAM. The SOT-MRAM stack may include a heavy metal spin hall effect rail configured to flip an SOT free-layer magnetic orientation in response to a horizontal signal through the heavy metal rail.

A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.

Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

Various embodiments provide a triaxial magnetic sensor, formed on or in a substrate of semiconductor material having a surface that includes a sensing portion and at least one first and one second sensing wall, which are not coplanar to each other. The sensing portion and the first sensing wall form a first solid angle, the sensing portion and the second sensing wall form a second solid angle, and the first sensing wall and the second sensing wall form a third solid angle. A first Hall-effect magnetic sensor extends at least partially over the sensing portion, a second Hall-effect magnetic sensor extends at least partially over the first sensing wall, and a third Hall-effect magnetic sensor extends at least partially over the second sensing wall.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a memory cell overlying a substrate. A lower via underlies the memory cell. The lower via is laterally offset from the memory cell by a lateral distance. A first conductive layer is disposed vertically between the memory cell and the lower via and comprising a first material. The first conductive layer continuously extends along the lateral distance. A second conductive layer extends across an upper surface of the first conductive layer and comprises a second material different from the first material. A bottom surface of the second conductive layer is aligned with a bottom surface of the memory cell.

A magnetization rotation element includes: a spin-orbit torque wiring; a first ferromagnetic layer laminated on the spin-orbit torque wiring; and a low resistance layer laminated on a region that does not overlap the first ferromagnetic layer when viewed in a laminating direction of the spin-orbit torque wiring, the spin-orbit torque wiring includes a first region, a second region, and a third region, the first region overlaps the first ferromagnetic layer when viewed in the laminating direction, the second region does not overlap the first ferromagnetic layer and the low resistance layer when viewed in the laminating direction and is located between the first region and the third region, the third region overlaps the low resistance layer when viewed in the laminating direction, a resistivity of the low resistance layer is lower than that of the spin-orbit torque wiring, and the low resistance layer is thinner than the spin-orbit torque wiring.

A magnetization rotation element includes: a spin-orbit torque wiring; a first ferromagnetic layer laminated on the spin-orbit torque wiring; and a low resistance layer laminated on a region that does not overlap the first ferromagnetic layer when viewed in a laminating direction of the spin-orbit torque wiring, the spin-orbit torque wiring includes a first region, a second region, and a third region, the first region overlaps the first ferromagnetic layer when viewed in the laminating direction, the second region does not overlap the first ferromagnetic layer and the low resistance layer when viewed in the laminating direction and is located between the first region and the third region, the third region overlaps the low resistance layer when viewed in the laminating direction, a resistivity of the low resistance layer is lower than that of the spin-orbit torque wiring, and the low resistance layer is thinner than the spin-orbit torque wiring.

Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.

Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.