A semiconductor memory device is disclosed. The semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor.

A semiconductor memory device is disclosed. The semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor.

Disclosed is a magnetic field-free spin-orbit torque switching device including a sapphire miscut substrate. More particularly, a spin-orbit torque switching device according to an embodiment includes a substrate having a step-terrace structure; and an input device formed on the substrate and provided with a heavy metal layer HM and a ferromagnetic layer FM.

Disclosed is a magnetic field-free spin-orbit torque switching device including a sapphire miscut substrate. More particularly, a spin-orbit torque switching device according to an embodiment includes a substrate having a step-terrace structure; and an input device formed on the substrate and provided with a heavy metal layer HM and a ferromagnetic layer FM.

A magnetic memory device includes a magnetic track extending in a first direction. The magnetic track includes a lower magnetic layer, an upper magnetic layer on the lower magnetic layer, a non-magnetic pattern on the lower magnetic layer and at a side of the upper magnetic layer, and a spacer layer between the lower magnetic layer and the upper magnetic layer and extending between the lower magnetic layer and the non-magnetic pattern. The lower magnetic layer and the upper magnetic layer are antiferromagnetically coupled to each other by the spacer layer. The non-magnetic pattern has a first surface and a second surface which are opposite to each other in a second direction perpendicular to the first direction. A junction surface between the non-magnetic pattern and the upper magnetic layer is inclined with respect to a reference surface perpendicular to the first surface and the second surface.

A magnetic memory device includes a magnetic track extending in a first direction. The magnetic track includes a lower magnetic layer, an upper magnetic layer on the lower magnetic layer, a non-magnetic pattern on the lower magnetic layer and at a side of the upper magnetic layer, and a spacer layer between the lower magnetic layer and the upper magnetic layer and extending between the lower magnetic layer and the non-magnetic pattern. The lower magnetic layer and the upper magnetic layer are antiferromagnetically coupled to each other by the spacer layer. The non-magnetic pattern has a first surface and a second surface which are opposite to each other in a second direction perpendicular to the first direction. A junction surface between the non-magnetic pattern and the upper magnetic layer is inclined with respect to a reference surface perpendicular to the first surface and the second surface.

A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.

A physically unclonable function is an object that has characteristics that make it extremely difficult or impossible to copy. An array of randomly dispersed hard (magnetized) and soft (non-magnetized) magnetic particles that may be conducting or nonconducting that are disbursed in a binder create a particular magnetic field or capacitive pattern on the surface. This surface magnetic field and capacitive variations can be considered to be a unique pattern similar to fingerprint. The Hall effect prism is a sensor that measures the effects of these patterns by sensing the deformation of currents or electric potential flowing within or around a resistive substrate material that exhibits a substantial Hall effect coefficient.

Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.