A memory cell is disclosed which includes a semiconductor layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another along a first axis and wherein the semiconductor layer extends beyond the first axis along a second axis substantially perpendicular to the first axis, thereby forming a first wing, a third electrode separated from the semiconductor layer by an insulating layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.

The present disclosure generally relates to a SOT-MRAM cell that has a spin Hall effect layer and a magnetic tunnel junction. The magnetic tunnel junction is disposed at an edge of the spin Hall effect layer. In order to write the cell, current is applied through the spin Hall effect layer to create spin accumulation of z-polarized spins under the free layer due to the spin Hall effect. The spins exert a spin torque on the free layer via spin diffusion. Based upon the design, the SOT-MRAM cell has deterministic switching of the perpendicular free layer with the spin Hall effect layer without application of an external magnetic field.

A spin-current magnetization rotational element includes a spin orbit torque wiring extending in a first direction and a first ferromagnetic layer disposed in a second direction intersecting the first direction of the spin orbit torque wiring, the spin orbit torque wiring having a first surface positioned on the side where the first ferromagnetic layer is disposed, and a second surface opposite to the first surface, and the spin orbit torque wiring has a second region on the first surface outside a first region in which the first ferromagnetic layer is disposed, the second region being recessed from the first region to the second surface side.

A spin-current magnetization rotational element includes a spin orbit torque wiring extending in a first direction and a first ferromagnetic layer disposed in a second direction intersecting the first direction of the spin orbit torque wiring, the spin orbit torque wiring having a first surface positioned on the side where the first ferromagnetic layer is disposed, and a second surface opposite to the first surface, and the spin orbit torque wiring has a second region on the first surface outside a first region in which the first ferromagnetic layer is disposed, the second region being recessed from the first region to the second surface side.

A method for manufacturing a Hall sensor, an insulation layer being initially applied to a wafer including an ASIC or integrated into the wafer, a Hall layer, for example, made of InSb or another III-V semiconductor material, being situated thereon, and this Hall layer being at least sectionally recrystallized with the aid of a laser. The insulation layer may be porous or may include a cavity or reflective layer for thermal protection of the ASIC.

A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic random access memory (MRAM) region and a logic region, forming a first inter-metal dielectric (1MB) layer on the substrate, forming a first metal interconnection and a second metal interconnection in the first IMD layer on the MRAM region, forming a spin orbit torque (SOT) layer on the first metal interconnection and the second metal interconnection, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, forming a hard mask on the MTJ stack, using the hard mask to pattern the MTJ stack for forming the MTJ, forming the cap layer on the SOT layer and the hard mask, and patterning the cap layer and the SOT layer.

A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic random access memory (MRAM) region and a logic region, forming a first inter-metal dielectric (1MB) layer on the substrate, forming a first metal interconnection and a second metal interconnection in the first IMD layer on the MRAM region, forming a spin orbit torque (SOT) layer on the first metal interconnection and the second metal interconnection, forming a magnetic tunneling junction (MTJ) stack on the SOT layer, forming a hard mask on the MTJ stack, using the hard mask to pattern the MTJ stack for forming the MTJ, forming the cap layer on the SOT layer and the hard mask, and patterning the cap layer and the SOT layer.

A chip package, a chip package system, a method of manufacturing a chip package, and a method of operating a chip package including: a first sensor configured to measure a magnetic field component up to a maximum magnetic field value; a second sensor configured to measure the magnetic field component beyond the maximum magnetic field value; and a circuit coupled to the first sensor and the second sensor and configured to receive at least one sensor signal from at least one of the first sensor and the second sensor, wherein the circuit is further configured to select the first sensor or the second sensor to measure the magnetic field component based on the received sensor signal.

The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.

The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.