A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

To suppress a leakage current caused by a gate of a tunnel field effect transistor included in a silicon spin quantum bit device, the silicon spin quantum bit device is provided including a tunnel field effect transistor having a gate, a source, and a drain, a quantum gate operation mechanism for spin control, which is provided under the tunnel field effect transistor, and an inter-qubit coupler for coupling a channel of the tunnel field effect transistor with a channel of a tunnel field effect transistor included in another quantum bit device. Further, the gate is made wider in width than the channel and is partly formed on the inter-qubit coupler.

To suppress a leakage current caused by a gate of a tunnel field effect transistor included in a silicon spin quantum bit device, the silicon spin quantum bit device is provided including a tunnel field effect transistor having a gate, a source, and a drain, a quantum gate operation mechanism for spin control, which is provided under the tunnel field effect transistor, and an inter-qubit coupler for coupling a channel of the tunnel field effect transistor with a channel of a tunnel field effect transistor included in another quantum bit device. Further, the gate is made wider in width than the channel and is partly formed on the inter-qubit coupler.

An elementary cell for a two-dimensional array of quantum dots, said elementary cell extending along a main plane and including: a plurality of sites occupied by quantum dots capable of confining at least one spin qubit and including at least: a first quantum dot, a second quantum dot adjacent to the first quantum dot in a first direction of the main plane, and a third quantum dot adjacent to the first quantum dot in a second direction of the main plane; and a first blocking site adjacent to the second and third quantum dots, towards which a spin qubit cannot be displaced.

An elementary cell for a two-dimensional array of quantum dots, said elementary cell extending along a main plane and including: a plurality of sites occupied by quantum dots capable of confining at least one spin qubit and including at least: a first quantum dot, a second quantum dot adjacent to the first quantum dot in a first direction of the main plane, and a third quantum dot adjacent to the first quantum dot in a second direction of the main plane; and a first blocking site adjacent to the second and third quantum dots, towards which a spin qubit cannot be displaced.

An integration structure for connecting a plurality of semiconductor devices, includes a substrate, a first face and a second face for receiving the semiconductor devices. At the first surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. At the second surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. The integration structure includes at least one non-superconducting conductive via connecting a non-superconducting conductive routing track of the first face to a non-superconducting conductive track of the second face and/or at least one superconducting via connecting a superconducting routing track of the first face to a superconducting track of the second face.

According to various implementations of the invention, high quality a-axis XBCO may be grown with low surface roughness. According to various implementations of the invention, low surface roughness may be obtained by: 1) adequate substrate preparation; 2) calibration of flux rates for constituent atoms; and/or 3) appropriate control of temperature during crystal growth. According to various implementions of the invention, a wafer comprises a smoothing layer of c-axis XBCO; a first conducting layer of a-axis XBCO formed on the smoothing layer; an insulating layer formed on the first conducting layer; and a second conducting layer of a-axis XBCO formed on the insulating layer, where, for a same surface roughness, a thickness of the smoothing layer and the first conducting layer combined is greater than a thickness of the first conducting layer without the smoothing layer. According to various implementations of the invention, a Josephson Junction is etched out of the XBCO/insulating layer/XBCO trilayer by: ion mill etching the top XBCO layer and some of the insulating layer to intentionally leave some of the insulating layer on the bottom XBCO layer; and/or ion mill etching at least the insulating layer at an off angle to reduce or minimize ion damage to the bottom XBCO layer otherwise introduced by the ion mill.

A system and method for treating a cavity comprises arranging a niobium structure in a coating chamber, the coating chamber being arranged inside a furnace, coating the niobium structure with tin thereby forming an Nb.sub.3Sn layer on the niobium structure, and doping the Nb.sub.3Sn layer with nitrogen, thereby forming a nitrogen doped Nb.sub.3Sn layer on the niobium structure.

An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.