A vertical transmon qubit structure, includes a substrate having a first surface and a second surface. A through-silicon-via (TSV) is located in the substrate. A first electrode of a Josephson junction (JJ) is located on a portion of the first surface of the substrate and adjacent to the TSV. A second electrode of the JJ is in contact with the TSV and on a second portion of the first surface of the substrate. The first electrode is separated from the second electrode by an insulator.

Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.

A current limiter arrangement limiting an electric current between a first and a second terminal includes a first current limiting device and a second current limiting device arranged between the first and the second terminal. The first and the second current limiting device each include a substrate having a substrate surface area and a substrate thickness, and include a superconducting section arranged on the substrate and thermally coupled to the substrate thereby covering a coupling surface area on the substrate. Each of the superconducting sections has a critical current value and the substrate surface areas, the substrate thicknesses and or the coupling surface areas are implemented as a function of the critical current values.

A parametric traveling wave amplifier (200) is disclosed in which the amplifiers include: a co-planar waveguide, in which the co-planar waveguide includes at least one Josephson junction (210) interrupting a center trace (204) of the co-planar waveguide; and at least one shunt capacitor coupled to the co-planar waveguide, in which each shunt capacitor of the at least one shunt capacitor includes a corresponding superconductor trace (214) extending over an upper surface of the center trace of the co-planar waveguide, and in which a gap separates the superconductor trace from the upper surface of the center trace, and in which the co-planar waveguide including the at least one Josephson junction and the shunt capacitor establish a predefined overall impedance for the traveling wave parametric amplifier.

An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.

A polycrystalline bulk body of this invention has uniformity in superconducting properties, in comparison to a polycrystalline bulk body including crystal grains each constituted by (Ba.sub.1-xK.sub.x)Fe.sub.2As.sub.2. A polycrystalline bulk body (1) of this invention includes crystal grains each constituted by an iron-based compound (10) expressed by chemical formula AA′Fe.sub.4As.sub.4, where A is Ca and A′ is K, the iron-based compound (10) having a crystal structure in which AFe.sub.2As.sub.2 layers (16) and A′Fe.sub.2As.sub.2 layers (17) are alternately stacked.

The present invention relates to a precursor (1) for production of a high-temperature superconductor (HTS) in ribbon form, comprising a metallic substrate (10) in ribbon form having a first ribbon side (11) and a second ribbon side (12), wherein, on the first ribbon side (11), (a) the substrate (10) has a defined texture as template for crystallographically aligned growth of a buffer layer or an HTS layer and (b) an exposed surface of the substrate (10) is present or one or more layers (20,30) are present that are selected from the group consisting of: buffer precursor layer, pyrolyzed buffer precursor layer, buffer layer, HTS precursor layer, pyrolyzed HTS buffer precursor layer and pyrolyzed and further consolidated HTS buffer precursor layer, and, on the second ribbon side (12), at least one ceramic barrier layer (40) that protects the substrate (10) against oxidation or a precursor which is converted to such a layer during the HTS crystallization annealing or the pyrolysis is present, wherein, when one or more layers (20, 30) are present on the first ribbon side (11), the ceramic barrier layer (40) or the precursor thereof has a different chemical composition and/or a different texture than the layer (20) arranged on the first ribbon side (11) and directly adjoining the substrate (10). In this precursor, the barrier layer (40) is a layer that delays or prevents ingress of oxygen to the second ribbon side (12) and is composed of conductive ceramic material or a precursor which is converted to such a precursor during the HTS crystallization annealing or the pyrolysis, and the ceramic material is an electrically conductive metal oxide or an electrically conductive mixture of metal oxides, wherein the conductive metal oxide or one or more metal oxides in the conductive mixture is/are preferably metal oxide(s) doped with an extraneous metal.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

This disclosure describes a superconducting device comprising a trench and a cavity that extends through a superconducting base layer. The trench crosses the cavity. The superconducting device further comprises a first junction layer that extends from a first region of the superconducting base layer to the cavity, an insulating layer on the surface of the first junction layer, and a second junction layer that extends from a second region of the superconducting base layer to the cavity. The second junction layer overlaps with the insulating layer on the bottom of the cavity. The disclosure also describes a method for producing this disclosed superconducting device.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.