A method of fabrication in a vacuum chamber. The method comprises: deploying the wafer within the vacuum chamber; applying a mask in a first position over the wafer in the vacuum chamber; following this, performing a first fabrication step comprising projecting material onto the wafer through the mask while in vacuum in the vacuum chamber; then operating a mask-handling mechanism deployed within the vacuum chamber in order to reposition the mask to a second position while remaining in vacuum in the vacuum chamber, wherein the repositioning comprises receiving readings from one or more sensors sensing a current position of the mask and based thereon aligning the current position of the mask to the second position; and following this repositioning, performing a second fabrication step comprising projecting material onto the wafer through patterned openings in the repositioned mask while still maintaining the vacuum in the vacuum chamber.

A system and method for treating a cavity comprises preparing a superconducting radio frequency (SRF) cavity for removal of a dielectric layer from on an inner surface of the SRF cavity, subjecting the SRF cavity to a heat treatment in order to remove the dielectric layer from the inner surface of the SRF cavity, and preventing the development of a new dielectric layer on the inner surface of the SRF cavity by preventing an interaction between the inner surface of the SRF cavity and atmospheric gasses.

A system and method for treating a cavity comprises preparing a superconducting radio frequency (SRF) cavity for removal of a dielectric layer from on an inner surface of the SRF cavity, subjecting the SRF cavity to a heat treatment in order to remove the dielectric layer from the inner surface of the SRF cavity, and preventing the development of a new dielectric layer on the inner surface of the SRF cavity by preventing an interaction between the inner surface of the SRF cavity and atmospheric gasses.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same are described. An example semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, where each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a selected surface of the semiconductor heterostructure by a predetermined offset amount.

Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount. The method further includes forming a superconducting layer over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.

Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount. The method further includes forming a superconducting layer over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.

To provide a superconducting device capable of more accurately arranging a non-contact coupling circuit of a superconducting integrated circuit chip and a non-contact coupling circuit of a circuit board. The chip has a first electrode made of a first superconducting material and a first non-contact coupling circuit on a surface thereof. The board has a second electrode made of a second superconducting material and a second non-contact coupling circuit on a surface thereof, and is arranged to face the chip. The second electrode has a protrusion protruding toward the chip. The protrusion includes a flat upper surface. The first electrode has a flat surface and a first recess. The first recess is arranged to face the upper surface to be located inside the upper surface of the protrusion. A third superconducting material connecting the upper surface and the first recess.

To provide a superconducting device capable of more accurately arranging a non-contact coupling circuit of a superconducting integrated circuit chip and a non-contact coupling circuit of a circuit board. The chip has a first electrode made of a first superconducting material and a first non-contact coupling circuit on a surface thereof. The board has a second electrode made of a second superconducting material and a second non-contact coupling circuit on a surface thereof, and is arranged to face the chip. The second electrode has a protrusion protruding toward the chip. The protrusion includes a flat upper surface. The first electrode has a flat surface and a first recess. The first recess is arranged to face the upper surface to be located inside the upper surface of the protrusion. A third superconducting material connecting the upper surface and the first recess.

A production line device prepares a superconducting circuit layer on a substrate. The device prepares an under bump metallization (UBM) layer on an upper surface of the superconducting circuit layer. A superconducting connection is formed between the UBM layer and the superconducting circuit layer. The production device prepares a welding spot on an upper surface of the UBM layer to obtain a qubit assembly configured for a flip-chip superconducting quantum chip. A superconducting electrical connection is formed between the welding spot and the UBM layer.