A production line device prepares a superconducting circuit layer on a substrate. The device prepares an under bump metallization (UBM) layer on an upper surface of the superconducting circuit layer. A superconducting connection is formed between the UBM layer and the superconducting circuit layer. The production device prepares a welding spot on an upper surface of the UBM layer to obtain a qubit assembly configured for a flip-chip superconducting quantum chip. A superconducting electrical connection is formed between the welding spot and the UBM layer.

A shadow wall for controlling directional deposition of a material is arranged on a substrate. The shadow wall comprises a base portion and a bridge portion. The base portion is arranged on the substrate and is configured to support the bridge portion. The bridge portion overhangs the substrate. The shadow wall may have improved compatibility with non-directional deposition processes, because adatoms on the surface of the substrate may diffuse under the bridge. Also provided are a method of fabricating a device using the shadow wall, and a method of fabricating the shadow wall.

A Josephson junction comprises superconducting electrodes (20) interconnected via an intermediate Josephson barrier (22), wherein the superconducting electrodes (20) and the intermediate Josephson barrier (22) are made out of the same chemical elements and are in a pristine condition.

Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.

Described is a method comprising directing an ultra-low voltage electron beam to a surface of a first insulating layer. The first insulating layer is disposed on a second insulating layer. The method includes modifying, by the application of the ultra-low voltage electron beam, the surface of the first insulating layer to selectively switch an interface between a first state having a first electronic property and a second state having a second electronic property.

A method for fabricating a second generation high-temperature superconductor (2G-HTS) tape, including: (S1) depositing a superconducting thin film on a surface of a ductile metal substrate with a buffer layer; (S2) forming a micro-holes array pattern on a surface of the superconducting thin film by etching using a reel-to-reel dynamic femtosecond infrared laser etching system, where the micro-holes array pattern covers the superconducting thin film; (S3) depositing a superconducting thick film on the surface of the superconducting thin film; and (S4) depositing a silver protective layer and a copper stabilization layer on a surface of the superconducting thick film.

A method of fabricating semiconductor-superconductor nanowires, comprising: forming a first mask amorphous mask having first openings over trenches in a substrate; forming a monocrystalline conducting material in the first openings by selective area growth, thus forming gates for the nanowires in the trenches pf the substrate; forming a second mask over the substrate and gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer in the second openings; forming a crystalline semiconductor material on the buffer in the second openings by selective area growth in order to form the cores of the nanowires, wherein the gates intersect with the cores in the plane of the substrate; and forming the coating of superconductor material over at least part of each of the cores.

A method of fabricating semiconductor-superconductor nanowires, comprising: forming a first mask amorphous mask having first openings over trenches in a substrate; forming a monocrystalline conducting material in the first openings by selective area growth, thus forming gates for the nanowires in the trenches pf the substrate; forming a second mask over the substrate and gates, the second mask also being amorphous and having a pattern of second openings; forming an insulating crystalline buffer in the second openings; forming a crystalline semiconductor material on the buffer in the second openings by selective area growth in order to form the cores of the nanowires, wherein the gates intersect with the cores in the plane of the substrate; and forming the coating of superconductor material over at least part of each of the cores.

One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.

One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.