Patent classifications
H10N60/10
CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES
Among other things, an apparatus comprises quantum units; and couplers among the quantum units. Each coupler is configured to couple a pair of quantum units according to a quantum Hamiltonian characterizing the quantum units and the couplers. The quantum Hamiltonian includes quantum annealer Hamiltonian and a quantum governor Hamiltonian. The quantum annealer Hamiltonian includes information bearing degrees of freedom. The quantum governor Hamiltonian includes non-information bearing degrees of freedom that are engineered to steer the dissipative dynamics of information bearing degrees of freedom.
SUPERCONDUCTING ELECTROMAGNETIC WAVE SENSOR
An electromagnetic sensor for use in a variety of applications requiring extremely high sensitivity, such as measuring power and characteristics of incident electromagnetic radiation includes a superconducting layer that carries an exchange field for providing a spin splitting effect of charge carriers in the superconducting layer, a metal electrode, and an insulating layer arranged between the superconducting layer and metal electrode to form a spin filter junction therebetween. The electromagnetic sensor provides an antenna including a wave collecting element, in contact with the superconducting layer to convey thereinto external electromagnetic waves that are generated by an external source. An electric measurement device provides an output signal responsive to the amplitude and frequency of the external electromagnetic waves, and contacts the metal electrode to measure an electric current or voltage caused by the spin splitted charge carrier flow from the superconducting layer through the spin filter junction into the metal electrode.
QUANTUM BIT DEVICE
A quantum bit device according to the present invention includes a first quantum bit substrate 10 which includes a first superconductive wiring 13 disposed to have a magnetically coupled portion with a first superconductive magnetic flux quantum bit 14 on a surface thereof, a second quantum bit substrate 11 which includes a second superconductive wiring 13 disposed to have a magnetically coupled portion with a second superconductive magnetic flux quantum bit 14 on a surface thereof, and a base substrate 12 which includes a third superconductive wiring 13 configured by two superconductive wirings extending parallel to each other on a surface thereof. The first and second quantum bit substrates are placed on the base substrate, two end portions of the first superconductive wiring and two end portions on one side of the third superconductive wiring are joined via superconductive solders 15, two end portions of the second superconductive wiring and two end portions on the other side of the third superconductive wiring are joined via superconductive solders 15, and three of the first to third superconductive wirings form one continuous superconductive loop.
CRYOGENIC REFRIGERATION FOR LOW TEMPERATURE DEVICES
A method for fabricating an active cooling structure, comprising forming an array of Superconductor-Insulator-Normal Metal (NIS) tunnel structures between a non-conducting layer and a superconducting layer. The non-superconducting layer may comprise a plurality of non-superconducting traces running in a first direction. The superconductor layer may comprise a plurality of superconducting traces running in a second direction.
CRYOGENIC REFRIGERATION FOR LOW TEMPERATURE DEVICES
An active cooling structure, comprising a non-superconducting layer, a superconducting layer, and an array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions. The non-superconducting layer may comprise a plurality of non-superconducting traces. The superconducting layer may comprise a plurality of superconducting traces. The array of Superconductor-Insulator-Normal Metal (NIS) tunnel junctions may be located between the plurality of non-superconducting traces and the plurality of superconducting traces.
Forming semiconductor-superconductor hybrid devices with a horizontally-confined channel
Methods of forming semiconductor-superconductor hybrid devices with a horizontally-confined channel are described. An example method includes forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure. The method further includes forming a left gate adjacent to a first side of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure. The method further includes forming a right gate adjacent to a second side, opposite to the first side, of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure, where a top surface of each of the left gate and the right gate is offset vertically from a selected surface of each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure by a predetermined offset amount. The method further includes forming a superconducting layer over each of the first isolated semiconductor heterostructure and the second isolated semiconductor heterostructure.
Superconducting logic element
A superconducting logic element includes a superconducting tunnel junction including first and second superconductors. First and second insulating ferromagnets in contact with the first and second superconductors, respectively, generate by magnetic proximity effect a predetermined density of spin-split states in the first and second superconductors, respectively. A writing element applies a writing current to at least a superconductor and is in contact with one of the first or second insulating ferromagnets, so that the first and second insulating ferromagnets commute, by the magnetic field generated by the applied writing current, between a state with parallel magnetization to a state with antiparallel magnetization with respect to each other. The superconducting tunnel junction includes the first or second superconductor between which an insulating layer is arranged with tunnel barrier function, the insulating layer selected between a layer selected from the group consisting of AlOx, AlN, and the first or second insulating ferromagnet.
SEMICONDUCTOR AND FERROMAGNETIC INSULATOR HETEROSTRUCTURE
A first aspect provides a topological quantum computing device comprising a network of semiconductor-superconductor nanowires, each nanowire comprising a length of semiconductor formed over a substrate and a coating of superconductor formed over at least part of the semiconductor; wherein at least some of the nanowires further comprise a coating of ferromagnetic insulator disposed over at least part of the semiconductor. A second aspect provides a method of fabricating a quantum or spintronic device comprising a heterostructure of semiconductor and ferromagnetic insulator, by: forming a portion of the semiconductor over a substrate in a first vacuum chamber, and growing a coating of the ferromagnetic insulator on the semiconductor by epitaxy in a second vacuum chamber connected to the first vacuum chamber by a vacuum tunnel, wherein the semiconductor comprises InAs and the ferromagnetic insulator comprises EuS.
Superconducting device
This disclosure describes a superconducting device comprising a trench and a cavity that extends through a superconducting base layer. The trench crosses the cavity. The superconducting device further comprises a first junction layer that extends from a first region of the superconducting base layer to the cavity, an insulating layer on the surface of the first junction layer, and a second junction layer that extends from a second region of the superconducting base layer to the cavity. The second junction layer overlaps with the insulating layer on the bottom of the cavity. The disclosure also describes a method for producing this disclosed superconducting device.
Superconducting device
This disclosure describes a superconducting device comprising a trench and a cavity that extends through a superconducting base layer. The trench crosses the cavity. The superconducting device further comprises a first junction layer that extends from a first region of the superconducting base layer to the cavity, an insulating layer on the surface of the first junction layer, and a second junction layer that extends from a second region of the superconducting base layer to the cavity. The second junction layer overlaps with the insulating layer on the bottom of the cavity. The disclosure also describes a method for producing this disclosed superconducting device.